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參數(shù)資料
| 型號： | AD9761 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual 10-Bit TxDAC with 23 Interpolation Filters(內(nèi)插濾波器的雙10位D/A轉(zhuǎn)換器) |
| 中文描述： | 雙10與23位插值濾波器TxDAC系列（內(nèi)插濾波器的雙10位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 294K |
| 代理商： | AD9761 |
AD9761
–11–
REV. 0
Referring to Figure 23, the “new” first image associated with the
DAC’s higher data rate
after
interpolation is “pushed” out fur-
ther relative to the input signal. T he “old” first image associated
with the lower DAC data rate
before
interpolation is suppressed
by the digital filter. As a result, the transition band for the ana-
log reconstruction filter is increased thus reducing the complex-
ity of the analog filter.
T he digital interpolation filters for I and Q paths are identical
43 tap halfband symmetric FIR filters. Each filter receives de-
interleaved I or Q data from the digital input interface. T he
input CLOCK signal is internally divided by two to generate the
filter clock. T he filters are implemented with two parallel paths
running at the filter clock rate. T he output from each path is
selected on opposite phases of the filter clock, thus producing
interpolated filtered output data at the input clock rate. T he
frequency response and impulse response of these filters are
shown in Figures 2a and 2b. T able I lists the idealized filter
coefficients that correspond to the filter’s impulse response.
T he digital section of the AD9761 also includes an input inter-
face section designed to support interleaved I and Q input data
from a single 10-bit bus. T his section de-interleaves the I and Q
input data while ensuring its proper pairing for the 2
×
interpola-
tion filters. A SLEEP/RESET input serves a dual function by
providing a reset function for this section as well as providing
power down functionality. Refer to the DIGIT AL INPUT AND
INT ERFACE CONSIDERAT IONS and SLEEP/RESET
sections for a more detailed discussion.
DAC T RANSFE R FUNCT ION
Each I and Q DAC provides complementary current output
pins: IOUT (A/B) and QOUT (A/B) respectively. Note, QOUT A
and QOUT B operate identically to IOUT A and IOUT B.
IOUT A will provide a near full-scale current output, I
OUT FS
,
when all bits are high (i.e., DAC CODE = 1023) while IOUT B,
the complementary output, provides no current. T he current
output of IOUT A and IOUT B are a function of both the input
code and I
OUT FS
and can be expressed as:
I
IOUTA
= (
DAC CODE
/1024)
×
I
OUTFS
(1)
I
IOUTB
= (1023 –
DAC CODE
)/1024
×
I
OUTFS
where:
DAC CODE
= 0 to 1023 (i.e., Decimal Representation).
As previously mentioned, I
OUT FS
is a function of the reference
current, I
REF
, which is nominally set by a reference, V
REFIO
, and
external resistor, R
SET
. It can be expressed as:
I
OUTFS
= 16
×
I
REF
where:
I
REF
=
V
REFIO
/
R
SET
T he two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUT A
and IOUT B should be directly connected to matching resistive
loads, R
LOAD
, which are tied to analog common, ACOM. Note,
R
LOAD
represents the equivalent load resistance seen by IOUT A
or IOUT B. T he single-ended voltage output appearing at IOUT A
and IOUT B pins is simply:
V
IOUTA
= I
IOUTA
×
R
LOAD
V
IOUTB
= I
IOUTB
×
R
LOAD
(2)
(3)
(4)
(5)
(6)
Note, the full-scale value of V
IOUT A
and V
IOUT B
should not
exceed the specified output compliance range to maintain speci-
fied distortion and linearity performance.
T he differential voltage, V
IDIFF
, appearing across IOUT A and
IOUT B is:
V
IDIFF
=(
I
IOUTA
– I
IOUTB
)
×
R
LOAD
Substituting the values of I
IOUT A
, I
IOUT B
, and I
REF
; V
IDIFF
can be
expressed as:
V
IDIFF
={(2
DAC CODE
– 1023)/1024)}
×
(16
R
LOAD
/R
SET
)
×
V
REFIO
T hese last two equations highlight some of the advantages of
operating the AD9761 differentially. First, differential operation
will help cancel common-mode error sources associated with
I
IOUT A
and I
IOUT B
such as noise and distortion. Second, the
differential code dependent current and subsequent voltage,
V
IDIFF
, is twice the value of the single-ended voltage output (i.e.,
V
IOUT A
or V
IOUT B
) thus providing twice the signal power to the
load.
(7)
(8)
RE FE RE NCE OPE RAT ION
T he AD9761 contains an internal 1.20 V bandgap reference
which can be easily disabled and overridden by an external
reference. REFIO serves as either an
input or output
depending
on whether the internal or an external reference is selected. If
REFLO is tied to ACOM as shown in Figure 24, the internal
reference is activated and REFIO provides a 1.20 V output. In
this case, the internal reference must be filtered externally with a
ceramic chip capacitor of 0.1
μ
F or greater from REFIO to
REFLO. Also, REFIO should be buffered with an external
amplifier having a low input bias current (i.e., <1
μ
A) if any
additional loading is required.
50pF
CURRENT
SOURCE
ARRAY
+1.2V REF
REFIO
FS ADJ
REFLO
COMP2
AVDD
0.1 F
R
SET
2k
0.1 F
OPTIONAL EXTERNAL
REF BUFFER FOR
ADDITIONAL LOADS
COMPENSATION
CAPACITOR
REQUIRED
AD9761
Figure 24. Internal Reference Configuration
T he internal reference can also be disabled by connecting REFLO
to AVDD. In this case, an external reference may then be ap-
plied to REFIO as shown in Figure 25. T he external reference
may provide either a fixed reference voltage to enhance accuracy
and drift performance or a varying reference voltage for gain
control. Note that the 0.1
μ
F compensation capacitor is not
required since the internal reference is disabled and the high
input impedance (i.e., 1 M
) of REFIO minimizes any loading
of the external reference
.
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