參數(shù)資料
型號(hào): AD9760ARU
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: 10-Bit, 125 MSPS TxDAC D/A Converter
中文描述: PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28
封裝: 0.170 INCH, TSSOP-28
文件頁(yè)數(shù): 5/23頁(yè)
文件大?。?/td> 412K
代理商: AD9760ARU
AD9760
5
REV. B
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
28
27
26
25
24
23
22
21
NC = NO CONNECT
(MSB) DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
NC
NC
NC
CLOCK
DVDD
DCOM
NC
AVDD
COMP2
I
OUTA
I
OUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
TOP VIEW
(Not to Scale)
AD9760
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1
2–9
10
11–14, 25 NC
15
DB9
DB8–DB1
DB0
Most Significant Data Bit (MSB).
Data Bits 1–8.
Least Significant Data Bit (LSB).
No Internal Connection.
Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if
not used.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1
μ
F capacitor to ACOM when internal reference activated.
Full-Scale Current Output Adjust.
Bandwidth/Noise Reduction Node. Add 0.1
μ
F to AVDD for optimum performance.
Analog Common.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1
μ
F capacitor.
Analog Supply Voltage (+2.7 V to +5.5 V).
Digital Common.
Digital Supply Voltage (+2.7 V to +5.5 V).
Clock Input. Data latched on positive edge of clock.
SLEEP
16
17
REFLO
REFIO
18
19
20
21
22
23
24
26
27
28
FS ADJ
COMP1
ACOM
I
OUTB
I
OUTA
COMP2
AVDD
DCOM
DVDD
CLOCK
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