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參數資料
| 型號： | AD9754-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit, 125 MSPS High Performance TxDAC D/A Converter |
| 中文描述： | 14位，125 MSPS的TxDAC系列高性能D / A轉換 |
| 文件頁數： | 13/24頁 |
| 文件大?。?/td> | 327K |
| 代理商： | AD9754-EB |
AD9754
–13–
REV. A
INPUT CLOCK AND DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9754 is positive edge triggered, and
so exhibits SNR sensitivity when the data transition is close to
this edge. In general, the goal when applying the AD9754 is to
make the data transitions close to the negative clock edge. This
becomes more important as the sample rate increases. Figure 23
shows the relationship of SNR to clock placement.
TIME (ns) OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE
68
–8
S
64
60
56
52
48
44
40
–6
–4
–2
0
2
4
6
8
10
F
S
= 125MSPS
F
S
= 65MSPS
Figure 23. SNR vs. Clock Placement @ f
OUT
= 10 MHz
SLEEP MODE OPERATION
The AD9754 has a power-down function that turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 2.7 V to 5.5 V and
temperature range. This mode can be activated by applying a
logic level “1” to the SLEEP pin. This digital input also con-
tains an active pull-down circuit that ensures the AD9754 re-
mains enabled if this input is left disconnected. The AD9754
takes less than 50 ns to power down and approximately 5
μ
s to
power back up.
POWER DISSIPATION
The power dissipation, P
D
, of the AD9754 is dependent on
several factors, including: (1) AVDD and DVDD, the power
supply voltages; (2) I
OUTFS
, the full-scale current output; (3)
f
CLOCK
, the update rate; and (4) the reconstructed digital input
waveform. The power dissipation is directly proportional to the
analog supply current, I
AVDD
, and the digital supply current,
I
DVDD
. I
AVDD
is directly proportional to I
OUTFS,
as shown in
Figure 24, and is insensitive to f
CLOCK
.
Conversely, I
DVDD
is dependent on both the digital input wave-
form, f
CLOCK
, and digital supply DVDD. Figures 25 and 26
show I
DVDD
as a function of full-scale sine wave output ratios
(f
OUT
/f
CLOCK
) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note, how I
DVDD
is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3V.
I
OUTFS
– mA
35
52
20
4
6
8
10
12
14
16
18
30
25
20
15
10
I
A
Figure 24. I
AVDD
vs. I
OUTFS
RATIO (f
CLOCK
/f
OUT
)
18
16
0
0.01
1
0.1
I
D
8
6
4
2
12
10
14
5MSPS
25MSPS
50MSPS
100MSPS
125MSPS
Figure 25. I
DVDD
vs. Ratio @ DVDD = 5 V
RATIO (f
CLOCK
/f
OUT
)
8
0
0.01
1
0.1
I
D
6
4
2
5MSPS
25MSPS
50MSPS
100MSPS
125MSPS
Figure 26. I
DVDD
vs. Ratio @ DVDD = 3 V
相關PDF資料 |
PDF描述 |
|---|---|
| AD9754AR | 14-Bit, 125 MSPS High Performance TxDAC D/A Converter |
| AD9760ARU50 | 10-Bit, 125 MSPS TxDAC D/A Converter |
| AD9760 | 10-Bit, 125 MSPS TxDAC D/A Converter |
| AD9760-EB | 10-Bit, 125 MSPS TxDAC D/A Converter |
| AD9760AR | 10-Bit, 125 MSPS TxDAC D/A Converter |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9754-EBZ | 功能描述:BOARD EVAL FOR AD9754 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數模轉換器 (DAC) 系列:TxDAC® 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數量:4 位數:12 采樣率（每秒）:- 數據接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9755 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AD9755: 14-Bit. 300 MSPS High-Speed TxDAC+?D/A Converter Data Sheet (Rev. A. 1/03) |
| AD9755AST | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:14-BIT, 300 MSPS TXDAC+ D/A CONVERTER - Bulk 制造商:Analog Devices 功能描述:CONVERTOR DA ((NW)) |
| AD9755-AST | 制造商:Analog Devices 功能描述: |
| AD9755ASTRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:14-BIT, 300 MSPS TXDAC+ D/A CONVERTER - Tape and Reel |
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