- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1988 > AD9753ASTZRL (Analog Devices Inc)IC DAC 12BIT 300MSPS 48LQFP PDF資料下載
參數(shù)資料
| 型號： | AD9753ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/28頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT 300MSPS 48LQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 2,000 |
| 系列： | TxDAC+® |
| 設置時間： | 11ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 165mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 300M |
| 配用： | AD9753-EB-ND - BOARD EVAL FOR AD9753 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當前第26頁第27頁第28頁
REV. B
AD9753
–7–
TERMINOLOGY
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight
line drawn from zero to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s, minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Specified as the maximum change from the ambient (25
°C)
value to the value at either TMIN or TMAX. For offset and gain
drift, the drift is reported in ppm of full-scale range (FSR) per
degree Celsius. For reference drift, the drift is reported in ppm
per degree Celsius.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels (dB).
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Adjacent Channel Power Ratio (ACPR)
A ratio in dBc between the measured power within a channel
relative to its adjacent channel.
AD9753
IOUTA
IOUTB
SEGMENTED
SWITCHES FOR
DB0 TO DB11
DAC
FSADJ
REFIO
1.2V REF
CLK+
PLLLOCK
DIGITAL DATA INPUTS
0.1 F
RSET
2k
1k
50
MINI
CIRCUITS
T1-1T
TO ROHDE &
SCHWARZ
FSEA30
SPECTRUM
ANALYZER
DB0 – DB11
TEKTRONIX DG2020
OR
AWG2021 w/OPTION 4
LECROY 9210
PULSE GENERATOR
(FOR DATA RETIMING)
DCOM
PMOS CURRENT
SOURCE ARRAY
AVDD
3.0V TO 3.6V
DVDD
2–1 MUX
PORT 1 LATCH
DAC LATCH
ACOM
PORT 2 LATCH
CLK–
PLL
CIRCUITRY
PLLVDD
CLKVDD
RESET
LPF
CLKCOM
DIV0
DIV1
50
DB0 – DB11
MINI
CIRCUITS
T1-1T
1k
3.0V TO 3.6V
HP8644
SIGNAL
GENERATOR
PLL ENABLED
PLL DISABLED
Figure 2. Basic AC Characterization Test Setup
相關PDF資料 |
PDF描述 |
|---|---|
| AD9754AR | IC DAC 14BIT 125MSPS HP 28-SOIC |
| AD9760ARZ50 | IC DAC 10BIT 50MSPS 28-SOIC |
| AD9761ARS | IC DAC 10BIT DUAL 40MSPS 28-SSOP |
| AD9767ASTZRL | IC DAC 14BIT DUAL 125MSPS 48LQFP |
| AD976BN | IC ADC 16BIT 100KSPS 28-DIP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9753-EB | 功能描述:BOARD EVAL FOR AD9753 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9754 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 125 MSPS High Performance TxDAC D/A Converter |
| AD9754AR | 功能描述:IC DAC 14BIT 125MSPS HP 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9754ARRL | 制造商:Analog Devices 功能描述:DAC 1-CH 14-bit 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:14-BIT, 125 MSPS+ TXDAC D/A CONVERTER - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。