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參數(shù)資料
| 型號： | AD9753-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 300 MSPS High-Speed TxDAC+?? D/A Converter |
| 中文描述： | 12位，300 MSPS的高速TxDAC系列？？ D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 904K |
| 代理商： | AD9753-EB |
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REV. 0
AD9753
–9–
FUNCTIONAL DESCRIPTION
Figure 3 shows a simplified block diagram of the AD9753. The
AD9753 consists of a PMOS current source array capable of
providing up to 20 mA of full-scale current, I
OUTFS
. The array is
divided into 31 equal sources that make up the five most signifi-
cant bits (MSBs). The next four bits, or middle bits, consist of
15 equal current sources whose value is 1/16th of an MSB cur-
rent source. The remaining LSBs are a binary weighted fraction
of the middle bit current sources. Implementing the middle
and lower bits with current sources, instead of an R-2R ladder,
enhances dynamic performance for multitone or low-amplitude
signals and helps maintain the DAC’s high output impedance
(i.e., >100 k
).
All of the current sources are switched to one or the other of the
two outputs (i.e., I
OUTA
or I
OUTB
) via PMOS differential current
switches. The switches are based on a new architecture that
drastically improves distortion performance. This new switch
architecture reduces various timing errors and provides match-
ing complementary drive signals to the inputs of the differential
current switches.
The analog and digital sections of the AD9753 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3.1 V to 3.5 V range. The digital section,
which is capable of operating at a 300 MSPS clock rate, consists
of edge-triggered latches and segment decoding logic circuitry.
The analog section includes the PMOS current sources, the
associated differential switches, a 1.20 V bandgap voltage refer-
ence and a reference control amplifier.
The full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, R
SET
. The external resistor, in combination
with both the reference control amplifier and voltage reference
V
REFIO
, sets the reference current I
REF
, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current, I
OUTFS
, is 32 times the value of I
REF
.
AD9753
I
OUTA
I
OUTB
SEGMENTED
SWITCHES FOR
DB0 TO DB11
DAC
FSADJ
REFIO
1.2V REF
DIV0
PLLLOCK
DIGITAL DATA INPUTS
0.1 F
R
SET
2k
R
LOAD
50
DB0
–
DB11
DCOM
PMOS CURRENT
SOURCE ARRAY
AVDD
3.1V TO 3.5V
DVDD
2-1 MUX
PORT 1 LATCH
DAC LATCH
ACOM
PORT 2 LATCH
DIV1
PLL
CIRCUITRY
PLLVDD
CLKVDD
CLK+
CLK
–
CLKCOM
RESET
LPF
DB0
–
DB11
V
OUT
B
R
LOAD
50
V
OUT
A
V
DIFF
= V
OUT
A
–
V
OUT
B
Figure 3. Simplified Block Diagram
REFERENCE OPERATION
The AD9753 contains an internal 1.20 V bandgap reference.
This can easily be overdriven by an external reference with no
effect on performance. REFIO serves as either an
input
or
output,
depending on whether the internal or an external reference is
used. To use the internal reference, simply decouple the REFIO
pin to ACOM with a 0.1
μ
F capacitor. The internal reference
voltage will be present at REFIO. If the voltage at REFIO is to
be used elsewhere in the circuit, an external buffer amplifier with
an input bias current less than 100 nA should be used. An example
of the use of the internal reference is given in Figure 4.
A low impedance external reference can be applied to REFIO as
shown in Figure 5. The external reference may provide either a
fixed reference voltage to enhance accuracy and drift performance
or a varying reference voltage for gain control. Note that the
0.1
μ
F compensation capacitor is not required since the internal
reference is overdriven, and the relatively high input impedance
of REFIO minimizes any loading of the external reference.
1.2V REF
AVDD
I
REF
CURRENT
SOURCE
ARRAY
REFIO
FSADJ
2k
0.1 F
AD9753
REFERENCE
SECTION
ADDITIONAL
EXTERNAL
LOAD
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
Figure 4. Internal Reference Configuration
1.2V REF
AVDD
I
REF
CURRENT
SOURCE
ARRAY
REFIO
FSADJ
2k
AD9753
REFERENCE
SECTION
EXTERNAL
REFERENCE
AVDD
Figure 5. External Reference Configuration
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相關(guān)代理商/技術(shù)參數(shù) |
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