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參數(shù)資料
| 型號： | AD9753-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 300 MSPS High-Speed TxDAC+?? D/A Converter |
| 中文描述： | 12位，300 MSPS的高速TxDAC系列？？ D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 12/26頁 |
| 文件大?。?/td> | 904K |
| 代理商： | AD9753-EB |
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REV. 0
AD9753
–12–
INTERLEAVED (2 ) MODE WITH PLL DISABLED
The relationship between the internal and external clocks in this
mode is shown in Figure 11. A clock at the output update data
rate (2
×
the input data rate) must be applied to the CLK inputs.
Internal dividers then create the internal 1
×
clock necessary for
the input latches. Although the input latches are updated on the
rising edge of the delayed internal 1
×
clock, the set-up-and-hold
times given in the Digital Specifications table are with respect to
the rising edge of the external 2
×
clock. With the PLL disabled,
a load-dependent delayed version of the 1
×
clock is present at
the PLLLOCK pin. This signal can be used to synchronize the
external data.
PORT 1
DATA IN
DATA X
DATA Y
t
H
t
S
t
LPW
t
PD
DATA X
DATA Y
PORT 2
I
OUTA
OR I
OUTB
DELAYED
INTERNAL
1 CLK
t
PD
t
D
DATA ENTERS
INPUT LATCHES
ON THIS EDGE
INTERNAL
2 CLK
EXTERNAL
1 CLK
@ PLLLOCK
Figure 11. Timing Requirements, Interleaved (2
×
) Mode
With PLL Disabled
Updates to the data at input Ports 1 and 2 should be synchro-
nized to the specific rising edge of the external 2
×
clock which
corresponds to the rising edge of the 1
×
internal clock as shown
in Figure 11. To ensure synchronization, a Logic “1” must be
momentarily applied to the RESET pin. Doing this and return-
ing RESET to Logic “0” brings the 1
×
clock at PLLLOCK to a
Logic “1.” On the next rising edge of the 2
×
clock, the 1
×
clock
will go to Logic “0.” On the second rising edge of the 2
×
clock,
the 1
×
clock (PLLLOCK) will again go to Logic “1,” as well as
update the data in both of the input latches. The details of this
are given in Figure 12.
RESET
PLLLOCK
EXTERNAL
2 CLOCK
t
RH
= 1.2ns
t
RS
= 0.2ns
DATA ENTERS
INPUT LATCHES
ON THESE EDGES
Figure 12. Reset Function Timing With PLL Disabled
For proper synchronization, sufficient delay must be present
between the time RESET goes low and the rising edge of the 2
×
clock. RESET going low must occur either at least t
RS
ns before
the rising edge of the 2
×
clock, or t
RH
ns afterwards. In the former
case, the immediately occurring CLK rising edge will cause
PLLLOCK to go low. In the latter case, the next CLK rising
edge will toggle PLLLOCK.
NONINTERLEAVED MODE WITH PLL DISABLED
If the data at only one port is required, the AD9753 interface
can operate as a simple double buffered latch with no interleaving.
On the rising edge of the 1
×
clock, input latch 1 or 2 is updated
with the present input data (depending on the state of DIV0/
DIV1). On the next rising edge, the DAC latch is updated and a
time t
PD
later, the DAC output reflects this change. Figure 13
represents the AD9753 timing in this mode.
t
H
t
S
t
LPW
t
PD
DATA OUT
PORT 1 OR
PORT 2
1 CLOCK
I
OUTA
OR I
OUTB
XX
DATA IN
PORT 1 OR
PORT 2
Figure 13. Timing Requirements, Noninterleaved Mode
with PLL Disabled
DAC TRANSFER FUNCTION
The AD9753 provides complementary current outputs, I
OUTA
and I
OUTB
. I
OUTA
will provide a near full-scale current output,
I
OUTFS
, when all bits are high (i.e., DAC CODE = 4095) while
I
OUTB
, the complementary output, provides no current. The
current output appearing at I
OUTA
and I
OUTB
is a function of
both the input code and I
OUTFS
, and can be expressed as:
I
OUTA
= (
DAC CODE
/4096)
×
I
OUTFS
I
OUTB
= (4095 –
DAC CODE
)/4096
×
I
OUTFS
where
DAC CODE
= 0 to 4095 (i.e., Decimal Representation).
As mentioned previously, I
OUTFS
is a function of the reference
current I
REF
, which is nominally set by a reference voltage,
V
REFIO
, and external resistor R
SET
. It can be expressed as:
I
OUTFS
= 32
×
I
REF
where
I
REF
=
V
REFIO
/
R
SET
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc-coupling is required, I
OUTA
and I
OUTB
should be directly connected to matching resistive
loads, R
LOAD
, that are tied to analog common, ACOM. Note,
R
LOAD
may represent the equivalent load resistance seen by
I
OUTA
or I
OUTB
as would be the case in a doubly terminated
50
or 75
cable. The single-ended voltage output appearing
at the I
OUTA
and I
OUTB
nodes is simply:
V
OUTA
=
I
OUTA
×
R
LOAD
V
OUTB
=
I
OUTB
×
R
LOAD
Note the full-scale value of
V
OUTA
and
V
OUTB
should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
V
DIFF
= (
I
OUTA
– I
OUTB
)
×
R
LOAD
Substituting the values of
I
OUTA
,
I
OUTB
and I
REF
;
V
DIFF
can be
expressed as:
V
DIFF
= {(2
DAC CODE
– 4095)/4096}
×
(32
R
LOAD
/
R
SET
)
×
V
REFIO
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
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