參數(shù)資料
型號(hào)： AD9751-EB
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/28頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR AD9751
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 1
位數(shù)： 10
采樣率（每秒）： 300M
數(shù)據(jù)接口： 并聯(lián)
設(shè)置時(shí)間： 11ns
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9751
相關(guān)產(chǎn)品： AD9751ASTZRL-ND - IC DAC 10BIT 300MSPS 48LQFP
AD9751ASTZ-ND - IC DAC 10BIT 300MSPS 48-LQFP
REV. C
AD9751
–15–
CLK–, can be driven from a single-ended or differential clock
source. For single-ended operation, CLK+ should be driven by
a logic source while CLK– should be set to the threshold voltage
of the logic source. This can be done via a resistor divider/
capacitor network, as shown in Figure 15a. For differential opera-
tion, both CLK+ and CLK– should be biased to CLKVDD/2
via a resistor divider network, as shown in Figure 15b.
Because the output of the AD9751 can be updated at up to
300 MSPS, the quality of the clock and data input signals are
important in achieving the optimum performance. The driv-
ers of the digital data interface circuitry should be specified
to meet the minimum setup-and-hold times of the AD9751 as
well as its required min/max input logic level thresholds.
Digital signal paths should be kept short and run lengths matched
to avoid propagation delay mismatch. Inserting a low value
resistor network (i.e., 20
to 100 ) between the AD9751 digi-
tal inputs and driver outputs may be helpful in reducing any
overshooting and ringing at the digital inputs that contribute to
data feedthrough. For longer run lengths and high data update
rates, strip line techniques with proper termination resistors
should be considered to maintain “clean” digital inputs.
The external clock driver circuitry should provide the AD9751
with a low jitter clock input, meeting the min/max logic levels
while providing fast edges. Fast clock edges help minimize any
jitter that manifests itself as phase noise on a reconstructed wave-
form. Thus, the clock input should be driven by the fastest logic
family suitable for the application.
The clock input could also be driven via a sine wave that is
centered around the digital threshold (i.e., DVDD/2) and meets
the min/max logic threshold. This typically results in a slight
degradation in the phase noise, which becomes more noticeable
at higher sampling rates and output frequencies. Also, at higher
sampling rates, the 20% tolerance of the digital logic threshold
should be considered since it affects the effective clock duty
cycle and, subsequently, cuts into the required data setup-and-
hold times.
RSERIES
0.1 F
VTHRESHOLD
CLK+
CLKVDD
CLK–
CLKCOM
AD9751
Figure 15a. Single-Ended Clock Interface
0.1 F
CLK+
CLKVDD
CLK–
CLKCOM
AD9751
0.1 F
Figure 15b. Differential Clock Interface
INPUT CLOCK AND DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9751 is rising edge triggered, and so
exhibits SNR sensitivity when the data transition is close to this
edge. In general, the goal when applying the AD9751 is to make
the data transition close to the falling clock edge. This becomes
more important as the sample rate increases. Figure 16 shows
the relationship of SNR to clock placement with different sample
rates. Note that the setup-and-hold times implied in Figure 16
appear to violate the maximums stated in the Digital Specifica-
tions table. The variation in Figure 16 is due to the skew present
between data bits inherent in the digital data generator used to
perform these tests. Figure 16 is presented to show the effects of
violating setup-and-hold times, and to show the insensitivity of
the AD9751 to clock placement when data transitions fall out-
side of the so-called “bad window.” The setup-and-hold times
stated in the Digital Specifications table were measured on a bit-
by-bit basis, therefore eliminating the skew present in the digital
data generator. At higher data rates, it becomes very important
to account for the skew in the input digital data when defining
timing specifications.
TIME OF DATA TRANSITION RELATIVE TO PLACEMENT OF
CLK RISING EDGE (ns), fOUT = 10MHz, fDAC = 300MHz
80
40
0
3
0
–3
SNR
(dBc)
60
20
70
30
50
10
–2
–1
1
2
Figure 16. SNR vs. Time of Data Transition Relative to
Clock Rising Edge
POWER DISSIPATION
The power dissipation, PD, of the AD9751 is dependent on sev-
eral factors that include the power supply voltages (AVDD and
DVDD), the full-scale current output IOUTFS, the update rate
fCLOCK, and the reconstructed digital input waveform. The power
dissipation is directly proportional to the analog supply current,
IAVDD, and the digital supply current, IDVDD. IAVDD is directly
proportional to IOUTFS, as shown in Figure 17, and is insensitive
to fCLOCK. Conversely, IDVDD is dependent on both the digital
input waveform, fCLOCK, and digital supply DVDD. Figure 18
shows IDVDD as a function of the ratio (fOUT/fDAC) for various
update rates. In addition, Figure 19 shows the effect the speed
of fDAC on the PLLVDD current, given the PLL divider ratio.
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