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參數(shù)資料
| 型號： | AD9751-EB |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 10-Bit, 300 MSPS High-Speed TxDAC+ D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, DAC WITH PROGRAMMABLE PLL, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 714K |
| 代理商： | AD9751-EB |
REV. 0
AD9751
–9–
FUNCTIONAL DESCRIPTION
Figure 3 shows a simplified block diagram of the AD9751. The
AD9751 consists of a PMOS current source array capable of
providing up to 20 mA of full-scale current, I
OUTFS
. The array is
divided into 31 equal sources that make up the five most signifi-
cant bits (MSBs). The next four bits, or middle bits, consist of
15 equal current sources whose value is 1/16th of an MSB cur-
rent source. The remaining LSB is a binary weighted fraction of
the middle bit current sources. Implementing the middle and
lower bits with current sources, instead of an R-2R ladder,
enhances dynamic performance for multitone or low-amplitude
signals and helps maintain the DAC’s high output impedance
(i.e., >100 k
).
All of the current sources are switched to one or the other of the
two outputs (i.e., I
OUTA
or I
OUTB
) via PMOS differential current
switches. The switches are based on a new architecture that
drastically improves distortion performance. This new switch
architecture reduces various timing errors and provides match-
ing complementary drive signals to the inputs of the differential
current switches.
The analog and digital sections of the AD9751 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3.1 V to 3.5 V range. The digital section,
which is capable of operating at a 300 MSPS clock rate, consists
of edge-triggered latches and segment decoding logic circuitry.
The analog section includes the PMOS current sources, the
associated differential switches, a 1.20 V bandgap voltage refer-
ence and a reference control amplifier.
The full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, R
SET
. The external resistor, in combination
with both the reference control amplifier and voltage reference
V
REFIO
, sets the reference current I
REF
, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current, I
OUTFS
, is 32 times the value of I
REF
.
REFERENCE OPERATION
The AD9751 contains an internal 1.20 V bandgap reference.
This can easily be overdriven by an external reference with no
effect on performance. REFIO serves as either an
input
or
output,
depending on whether the internal or an external reference is
used. To use the internal reference, simply decouple the REFIO
pin to ACOM with a 0.1
μ
F capacitor. The internal reference
voltage will be present at REFIO. If the voltage at REFIO is to
be used elsewhere in the circuit, an external buffer amplifier with
an input bias current less than 100 nA should be used. An example
of the use of the internal reference is given in Figure 4.
A low impedance external reference can be applied to REFIO
as shown in Figure 5. The external reference may provide either
a fixed reference voltage to enhance accuracy and drift perfor-
mance or a varying reference voltage for gain control. Note that
the 0.1
μ
F compensation capacitor is not required since the inter-
nal reference is overdriven, and the relatively high input impedance
of REFIO minimizes any loading of the external reference.
REFERENCE CONTROL AMPLIFIER
The AD9751 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, I
OUTFS
.
The control amplifier is configured as a voltage-to-current con-
verter as shown in Figure 4, so that its current output, I
REF
, is
determined by the ratio of V
REFIO
and an external resistor, R
SET
,
as stated in Equation 4. I
REF
is applied to the segmented current
sources with the proper scaling factor to set I
OUTFS
as stated in
Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
I
OUTFS
over a 2 mA to 20 mA range by setting I
REF
between
62.5
μ
A and 625
μ
A. The wide adjustment span of I
OUTFS
provides
several application benefits. The first benefit relates directly to
the power dissipation of the AD9751, which is proportional to
I
OUTFS
(refer to the Power Dissipation section). The second
benefit relates to the 20 dB adjustment, which is useful for sys-
tem gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency, small
signal multiplying applications.
AD9751
I
OUTA
I
OUTB
SEGMENTED
SWITCHES FOR
DB0 TO DB9
DAC
FSADJ
REFIO
1.2V REF
DIV0
PLLLOCK
DIGITAL DATA INPUTS
0.1 F
R
SET
2k
R
LOAD
50
DB0
–
DB9
DCOM
PMOS CURRENT
SOURCE ARRAY
AVDD
3.1V TO 3.5V
DVDD
2-1 MUX
PORT 1 LATCH
DAC LATCH
ACOM
PORT 2 LATCH
DIV1
PLL
CIRCUITRY
PLLVDD
CLKVDD
CLK+
CLK
–
CLKCOM
RESET
LPF
DB0
–
DB9
V
OUT
B
R
LOAD
50
V
OUT
A
V
DIFF
= V
OUT
A
–
V
OUT
B
Figure 3. Simplified Block Diagram
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9752 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 125 MSPS High Performance TxDAC D/A Converter |
| AD9752AR | 功能描述:IC DAC 12BIT 125MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC® 產品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9752ARRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 12-bit 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:12-BIT 125 MSPS+ TXDAC D/A CONVERTER - Tape and Reel |
| AD9752ARU | 功能描述:IC DAC 12BIT 125MSPS HP 28-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC® 產品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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