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參數(shù)資料
| 型號： | AD9751-EB |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 10-Bit, 300 MSPS High-Speed TxDAC+ D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, DAC WITH PROGRAMMABLE PLL, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 17/26頁 |
| 文件大?。?/td> | 714K |
| 代理商： | AD9751-EB |
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REV. 0
AD9751
–17–
AD9751
I
OUTA
I
OUTB
C
OPT
200
V
OUT
= I
OUTFS
R
FB
R
FB
200
Figure 24. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these applications, the
implementation and construction of the printed circuit board is
as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing, as well
as power supply bypassing and grounding, to ensure optimum
performance. Figures 34 to 41 illustrate the recommended
printed circuit board ground, power and signal plane layouts
which are implemented on the AD9751 evaluation board.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the Power Supply Rejection Ratio. For dc
variations of the power supply, the resulting performance of the
DAC directly corresponds to a gain error associated with the
DAC’s full-scale current, I
OUTFS
. AC noise on the dc supplies is
common in applications where the power distribution is gener-
ated by a switching power supply. Typically, switching power
supply noise will occur over the spectrum from tens of kHz to
several MHz. The PSRR vs. frequency of the AD9751 AVDD
supply over this frequency range is shown in Figure 25.
FREQUENCY
–
MHz
85
40
12
6
0
P
–
80
75
70
65
60
55
50
45
2
4
8
10
Figure 25. Power Supply Rejection Ratio
Note that the units in Figure 25 are given in units of (amps out/
volts in). Noise on the analog power supply has the effect of modu-
lating the internal switches, and therefore the output current.
The voltage noise on AVDD will thus be added in a nonlinear
manner to the desired I
OUT
. Due to the relative different size of
these switches, PSRR is very code-dependent. This can produce
a mixing effect that can modulate low frequency power supply
noise to higher frequencies. Worst-case PSRR for either one of
the differential DAC outputs will occur when the full-scale current
is directed toward that output. As a result, the PSRR measure-
ment in Figure 25 represents a worst-case condition in which
the digital inputs remain static and the full-scale output current
of 20 mA is directed to the DAC output being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV rms of noise and, for
simplicity sake (i.e., ignore harmonics), all of this noise is con-
centrated at 250 kHz. To calculate how much of this undesired
noise will appear as current noise superimposed on the DAC’s
full-scale current, I
OUTFS
, one must determine the PSRR in dB
using Figure 25 at 250 kHz. To calculate the PSRR for a given
R
LOAD
, such that the units of PSRR are converted from A/V to
V/V, adjust the curve in Figure 25 by the scaling factor 20
×
Log
(R
LOAD
). For instance, if R
LOAD
is 50
, the PSRR is reduced
by 34 dB (i.e., PSRR of the DAC at 250 kHz, which is 85 dB in
Figure 25, becomes 51 dB V
OUT
/V
IN
).
Proper grounding and decoupling should be a primary objective
in any high-speed, high-resolution system. The AD9751 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a sys-
tem. In general, AVDD, the analog supply, should be decoupled
to ACOM, the analog common, as close to the chip as physi-
cally possible. Similarly, DVDD, the digital supply, should be
decoupled to DCOM as close to the chip as physically possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 26. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.
AVDD
ACOM
100 F
ELECT.
10-22 F
TANT.
0.1 F
CER.
TTL/CMOS
LOGIC
CIRCUITS
3.3V
POWER SUPPLY
FERRITE
BEADS
Figure 26. Differential LC Filter for a Single 3.3 V Application
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9752 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 125 MSPS High Performance TxDAC D/A Converter |
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