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參數(shù)資料
| 型號： | AD9750 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit D/A Converter(100MSPS,10位D/A轉(zhuǎn)換器) |
| 中文描述： | 10位D / A轉(zhuǎn)換器（100MSPS時，10位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 14/21頁 |
| 文件大?。?/td> | 280K |
| 代理商： | AD9750 |
AD9750
–14–
REV. 0
PRELIMINARY
DATA
ential output of the AD9750 to midsupply (i.e., AVDD/2). The
AD8041 is a suitable op amp for this application.
TECHNICAL
AD9750
DIFFERENTIAL USING AN OP AMP
An op amp can also be used to perform a differential to single-
ended conversion as shown in Figure 32. The AD9750 is con-
figured with two equal load resistors, R
LOAD
, of 25
. The
differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB forming a real pole in a low-pass filter.
The addition of this capacitor also enhances the op amps distor-
tion performance by preventing the DACs high slewing output
from overloading the op amp’s input.
AD9750
IOUTA
IOUTB
C
OPT
500
V
225
V
225
V
500
V
25
V
AD8055
Figure 32. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differ-
ential op amp circuit is configured to provide some additional
signal gain. The op amp must operate off of a dual supply since
its output is approximately
±
1.0 V. A high speed amplifier such
as the AD8055 or AD8057 capable of preserving the differential
performance of the AD9750 while meeting other system level
objectives (i.e., cost, power) should be selected. The op amps
differential gain, its gain setting resistor values, and full-scale
output swing capabilities should all be considered when opti-
mizing this circuit.
The differential circuit shown in Figure 33 provides the neces-
sary level-shifting required in a single supply system. In this
case, AVDD which is the positive analog supply for both the
AD9750 and the op amp is also used to level-shift the differ-
AD9750
IOUTA
IOUTB
C
OPT
500
V
225
V
225
V
1k
V
25
V
25
V
AD8041
1k
V
AVDD
Figure 33. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 34 shows the AD9750 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly termi-
nated 50
cable since the nominal full-scale current, I
OUTFS
, of
20 mA flows through the equivalent R
LOAD
of 25
. In this
case, R
LOAD
represents the equivalent load resistance seen by
IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected to ACOM directly or via a matching R
LOAD
.
Different values of I
OUTFS
and R
LOAD
can be selected as long as
the positive compliance range is adhered to. One additional
consideration in this mode is the integral nonlinearity (INL) as
discussed in the ANALOG OUTPUT section of this data sheet.
For optimum INL performance, the single-ended, buffered
voltage output configuration is suggested.
AD9750
IOUTA
IOUTB
50
V
25
V
50
V
V
OUTA
= 0 TO +0.5V
I
OUTFS
= 20mA
Figure 34. 0 V to +0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 35 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the AD9750
output current. U1 maintains IOUTA (or IOUTB) at a virtual
on the DAC’s INL performance as discussed in the ANALOG
OUTPUT section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac distor-
tion performance at higher DAC update rates may be limited by
U1’s slewing capabilities. U1 provides a negative unipolar out-
put voltage and its full-scale output voltage is simply the
product of R
FB
and I
OUTFS
. The full-scale output should be set
within U1’s voltage output swing capabilities by scaling I
OUTFS
and/or R
FB
. An improvement in ac distortion performance may
result with a reduced I
since the signal current U1 will be
IOUTA
IOUTB
C
OPT
200
V
U1
V
OUT
= I
OUTFS
3
R
FB
I
OUTFS
= 10mA
R
FB
200
V
Figure 35. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS
In systems seeking to simultaneously achieve high speed and
high performance, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection;
placement and routing; and supply bypassing and grounding.
Figures 41–46 illustrate the recommended printed circuit board
ground, power and signal plane layouts which are implemented
on the AD9750 evaluation board.
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9750 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be de-
coupled to ACOM, the analog common, as close to the chip as
physically possible. Similarly, DVDD, the digital supply, should
be decoupled to DCOM as close as physically as possible.
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| AD9750AR | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 28-Pin SOIC W 制造商:Analog Devices 功能描述:DAC SGL 10-BIT 28SOIC - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:10 BIT 12500 MSPS+ TXDAC D/A CONVERTER - Bulk 制造商:Analog Devices 功能描述:0BIT DAC POLY FUSE 9750 SOIC28 |
| AD9750ARRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:10 BIT 125 MSPS+ TXDAC D/A CONVERTER - Bulk |
| AD9750ARU | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 28-Pin TSSOP 制造商:Rochester Electronics LLC 功能描述:10 BIT 125 MSPS+ TXDAC D/A CONVERTER - Bulk |
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