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參數(shù)資料
| 型號(hào)： | AD9750 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit D/A Converter(100MSPS,10位D/A轉(zhuǎn)換器) |
| 中文描述： | 10位D / A轉(zhuǎn)換器（100MSPS時(shí)，10位的D / A轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 12/21頁(yè) |
| 文件大?。?/td> | 280K |
| 代理商： | AD9750 |
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AD9750
–12–
REV. 0
DATA
V
THRESHOLD
= DVDD
/2 (
±
20%)
The internal digital circuitry of the AD9750 is capable of operating
over a digital supply range of 2.7 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers V
OH(MAX)
. A DVDD of 3 V to 3.3 V will typically ensure
proper compatibility with most TTL logic families. Figure 27
shows the equivalent digital input circuit for the data and clock
inputs. The sleep mode input is similar with the exception that
it contains an active pull-down circuit, thus ensuring that the
AD9750 remains enabled if this input is left disconnected.
TECHNICAL
SLEEP MODE OPERATION
The AD9750 has a power-down function which turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 2.7 V to 5.5 V and
temperature range. This mode can be activated by applying a
logic level “1” to the SLEEP pin. This digital input also con-
tains an active pull-down circuit that ensures the AD9750 re-
mains enabled if this input is left disconnected. The AD9750
takes less than 5
μ
s to power down and approximately TBD ms
to power back up.
In summary, the AD9750 achieves the optimum distortion and
noise performance under the following conditions:
(1) Differential Operation.
(2) Positive voltage swing at IOUTA and IOUTB limited to
+0.5 V.
(3) I
OUTFS
set to 20 mA.
(4) Analog Supply (AVDD) set at 5.0 V.
(5) Digital Supply (DVDD) set at 3.0 V to 3.3 V with appro-
priate logic levels.
Note that the ac performance of the AD9750 is characterized
under the above mentioned operating conditions.
DIGITAL INPUTS
The AD9750’s digital input consists of 10 data input pins and a
clock input pin. The 10-bit parallel data inputs follow standard
positive binary coding where DB9 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock as shown in Figure 1 and is designed to
support a clock rate as high as 125 MSPS. The clock can be
operated at any duty cycle that meets the specified latch pulse-
width. The set-up and hold times can also be varied within the
clock cycle as long as the specified minimum times are met;
although the location of these transition edges may affect digital
feedthrough and distortion performance.
Best performance is
typically achieved when the input data transitions on the falling edge
of a 50% duty cycle clock
.
The digital inputs are CMOS compatible with logic thresholds,
V
THRESHOLD
set to approximately half the digital positive supply
(DVDD) or
DVDD
DIGITAL
INPUT
Figure 27. Equivalent Digital Input
Since the AD9750 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. The drivers of the digital
data interface circuitry should be specified to meet the mini-
mum set-up and hold times of the AD9750 as well as its
required min/max input logic level thresholds. Typically, the
selection of the slowest logic family that satisfies the above con-
ditions will result in the lowest data feedthrough and noise.
Digital signal paths should be kept short and run lengths
matched to avoid propagation delay mismatch. The insertion of
a low value resistor network (i.e., 20
to 100
) between the
AD9750 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs that
contribute to data feedthrough. For longer run lengths and high
data update rates, strip line techniques with proper termination
resistors should be considered to maintain “clean” digital in-
puts. Also, operating the AD9750 with reduced logic swings and
a corresponding digital supply (DVDD) will also reduce data
feedthrough.
The external clock driver circuitry should provide the AD9750
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon-
structed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.
Note, the clock input could also be driven via a sine wave, which is
centered around the digital threshold (i.e., DVDD/2), and meets
the min/max logic threshold. This will typically result in a slight
degradation in the phase noise, which becomes more noticeable
sampling rates, the 20% tolerance of the digital logic threshold
should be considered since it will affect the effective clock duty
cycle and subsequently cut into the required data set-up and
hold times.
POWER DISSIPATION
The power dissipation, P
D
, of the AD9750 is dependent on
several factors which include: (1) AVDD and DVDD, the
power supply voltages; (2) I
OUTFS
, the full-scale current output;
(3) f
CLOCK
, the update rate; (4) and the reconstructed digital
input waveform. The power dissipation is directly proportional
to the analog supply current, I
AVDD
, and the digital supply cur-
rent, I
DVDD
. I
AVDD
is directly proportional to I
OUTFS
as shown in
Figure 28 and is insensitive to f
CLOCK
.
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|---|---|
| AD9750AR | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 28-Pin SOIC W 制造商:Analog Devices 功能描述:DAC SGL 10-BIT 28SOIC - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:10 BIT 12500 MSPS+ TXDAC D/A CONVERTER - Bulk 制造商:Analog Devices 功能描述:0BIT DAC POLY FUSE 9750 SOIC28 |
| AD9750ARRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:10 BIT 125 MSPS+ TXDAC D/A CONVERTER - Bulk |
| AD9750ARU | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 28-Pin TSSOP 制造商:Rochester Electronics LLC 功能描述:10 BIT 125 MSPS+ TXDAC D/A CONVERTER - Bulk |
| AD9750ARURL7 | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 28-Pin TSSOP T/R 制造商:Rochester Electronics LLC 功能描述:10 BIT 125 MSPS+ TXDAC D/A CONVERTER - Bulk |
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