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參數(shù)資料
| 型號(hào)： | AD9748ACPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/24頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT 210MSPS 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 系列： | TxDAC® |
| 設(shè)置時(shí)間： | 11ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 145mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 210M |
AD9748
Data Sheet
Rev. B | Page 8 of 24
TERMINOLOGY
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output increases or remains constant
as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For offset
and gain drift, the drift is reported in ppm of full-scale range (FSR)
per °C. For reference drift, the drift is reported in ppm per °C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified
bandwidth.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference
between the rms amplitude of a carrier tone to the peak
spurious signal in the region of a removed tone.
50
ROHDE & SCHWARZ
FSEA30
SPECTRUM
ANALYZER
MINI-CIRCUITS
T1-1T
*AWG2021 CLOCK
RETIMED SO THAT
THE DIGITAL DATA
TRANSITIONS ON
FALLING EDGE OF
50% DUTY CYCLE
CLOCK.
50
DVDD
DCOM
50
RETIMED
CLOCK
OUTPUT*
DIGITAL
DATA
TEKTRONIX AWG-2021
WITH OPTION 4
LECROY 9210
PULSE GENERATOR
CLOCK
OUTPUT
1.2V REF
3.3V
RSET
0.1
F
SLEEP
REFIO
FS ADJ
DVDD
DCOM
DIGITAL DATA INPUTS (DB7–DB0)
150pF
20pF
3.3V
AVDD
ACOM
AD9748
CURRENT
SOURCE
ARRAY
IOUTA
IOUTB
MODE
LSB
SWITCHES
SEGMENTED
SWITCHES
3.3V
CLKVDD
CLKCOM
CLK–
CLK+
CMODE
LATCHES
100
20pF
03211-004
Figure 4. Basic AC Characterization Test Setup (SOIC/TSSOP Packages)
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