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參數(shù)資料
| 型號： | AD9744ARURL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 14-Bit, 165 MSPS TxDAC D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 14-BIT DAC, PDSO28 |
| 封裝： | MO-153AE, TSSOP-28 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 1142K |
| 代理商： | AD9744ARURL7 |
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REV. A
–6–
AD9744
PIN CONFIGURATION
28-Lead SOIC and TSSOP
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9744
NC = NO CONNECT
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
(LSB) DB0
CLOCK
DVDD
DCOM
MODE
AVDD
RESERVED
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
DB10
DB11
DB12
(MSB) DB13
PIN FUNCTION DESCRIPTIONS
SOIC/TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic
Description
1
2–13
14
15
27
28–32, 1, 2, 4–8
9
25
DB13
DB12–DB1
DB0
SLEEP
Most Significant Data Bit (MSB).
Data Bits 12–1.
Least Significant Data Bit (LSB).
Power-Down Control Input. Active high. Contains active pull-down circuit;
it may be left unterminated if not used.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to
disable internal reference.
Reference Input/Output. Serves as reference input when internal reference disabled
(i.e., tie REFLO to AVDD). Serves as 1.2 V reference output when internal
reference activated (i.e., tie REFLO to ACOM). Requires 0.1
m
F capacitor to
ACOM when internal reference activated.
Full-Scale Current Output Adjust.
No Internal Connection.
Analog Common.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
RESERVED Reserved. Do Not Connect to Common or Supply.
AVDD
Analog Supply Voltage (3.3 V).
MODE
Selects Input Data Format. Connect to DCOM for straight binary, DVDD for
twos complement.
CMODE
Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver
(drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver.
Float for PECL receiver (terminations on-chip).
DCOM
Digital Common.
DVDD
Digital Supply Voltage (3.3 V).
CLOCK
Clock Input. Data latched on positive edge of clock.
CLK+
Differential Clock Input.
CLK–
Differential Clock Input.
CLKVDD
Clock Supply Voltage (3.3 V).
CLKCOM
Clock Common.
16
N/A
REFLO
17
23
REFIO
18
19
20
21
22
23
24
25
24
N/A
19, 22
20
21
N/A
17, 18
16
FS ADJ
NC
ACOM
IOUTB
IOUTA
N/A
15
26
27
28
N/A
N/A
N/A
N/A
10, 26
3
N/A
12
13
11
14
32-Lead LFCSP
PIN 1
INDICATOR
TOP VIEW
24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD
DB7 1
DB6 2
DVDD 3
DB5 4
DB4 5
DB3 6
DB2 7
DB1 8
3
(
D
C
C
C
C
C
M
3
3
2
2
2
2
AD9744
2
NC = NO CONNECT
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| AD9744ARUZ | 制造商:Analog Devices 功能描述:D/A CONVERTER (D-A) IC 制造商:Analog Devices 功能描述:IC, DAC, 14BIT, 210MSPS, TSSOP-28 |
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