- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373966 > AD9736-EB (Analog Devices, Inc.) 14/12/10-Bit, 1200 MSPS D/A Converters PDF資料下載
參數(shù)資料
| 型號： | AD9736-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14/12/10-Bit, 1200 MSPS D/A Converters |
| 中文描述： | 14/12/10-Bit，1200 MSPS的D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 30/42頁 |
| 文件大?。?/td> | 934K |
| 代理商： | AD9736-EB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
AD9736/AD9735/AD9734
Preliminary Technical Data
APPLICATIONS INFORMATION
Rev. PrJ | Page 30 of 42
FPGA/ASIC DAC DRIVER REQUIREMENTS
To achieve data synchronization using the high speed capability of
the AD9736, ADI recommends the configuration in Figure 35 for
the FPGA/ASIC driving the digital inputs. Using the Double Data
Rate DATACLK_OUT, this configuration will generate the LVDS
DATACLK_IN to drive the AD9736 at the DDR rate. The circuit
also synchronizes the DATACLK_IN and the digital input data
(DB<13:0>) as required by the AD9736. The synchronization
engine in the AD9736 then uses DATACLK_IN to generate the
internal CLOCK SAMPLING SIGNAL to capture the incoming
data via the Manual, Surveillance or Auto mode.
To operate in 2x mode, the circuit in Figure 35 must be modified to
include a divide-by-two block in the DATACLK_OUT path.
Without this additional divider the DATA and DATACLK_IN will
be running 2x too fast. DATACLK_OUT is always DACCLK/2.
Figure 35. Recommended FPGA/ASIC Configuration for Driving AD9736
Digital Inputs, 1x Mode
Figure 36. FPGA/ASIC Timing for Driving AD9736 Digital Inputs, 1x Mode
TIMING ERROR BUDGET
The following components make up the timing error budget for the
1.
2.
AD9736 DATACLK_OUT jitter
AD9736 DATACLK_IN jitter
3.
4.
5.
DB13:0 jitter
DB13:0 skew from data source
DB13:0 receiver skew margin (board + AD9736 internal
delays)
DB13:0 to DATACLK_IN skew from data source
6.
A
C
E
B
D
A
C
B
D
A
B
C
DATACLK_OUT+
DATA1
DATA2
D1
D2
DB
DATACLK_IN+
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9736BBC | 14/12/10-Bit, 1200 MSPS D/A Converters |
| AD974(中文) | 4-Channel, 16-Bit, 200 kSPS Data Acquisition System(4通道,200kSPS16位數(shù)據(jù)采集系統(tǒng)) |
| AD9740 | 10-Bit, 165 MSPS TxDAC D/A Converter |
| AD9740-EB | 10-Bit, 165 MSPS TxDAC D/A Converter |
| AD9740AR | 10-Bit, 165 MSPS TxDAC D/A Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9736-EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9735 DAC, 10-/12-/14BIT, 1200 MSPS DACS - Bulk |
| AD9736XBC | 制造商:Analog Devices 功能描述:14-BIT 1600 MSPS D/A CONVERTER - Bulk |
| AD9737A | 制造商:AD 制造商全稱:Analog Devices 功能描述:11-/14-Bit, 2.5 GSPS |
| AD9737ABBCZ | 功能描述:IC DAC 11BIT 2.5GSPS RF 160BGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD9737ABBCZRL | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 11-Bit 2.5 GSPS RF RoHS:否 制造商:Analog Devices 轉(zhuǎn)換器數(shù)量:4 DAC 輸出端數(shù)量:4 轉(zhuǎn)換速率: 分辨率:12 bit 接口類型:Serial (I2C) 穩(wěn)定時(shí)間: 最大工作溫度:+ 105 C 安裝風(fēng)格: 封裝 / 箱體:TSSOP 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。