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參數(shù)資料
| 型號： | AD9736-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14/12/10-Bit, 1200 MSPS D/A Converters |
| 中文描述： | 14/12/10-Bit，1200 MSPS的D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 26/42頁 |
| 文件大小： | 934K |
| 代理商： | AD9736-EB |
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AD9736/AD9735/AD9734
Preliminary Technical Data
Rev. PrJ | Page 26 of 42
OPERATION IN SURVEILLANCE AND AUTO MODES
Once FIFOSTAT<2:0> has been manually placed in an optimal
state the AD9736 SYNC logic can be run in Surveillance or Auto
mode. To start, turn on Surveillance mode by setting SSURV = 1
(REG08, bit 7) then enable the sync interrupt (REG01, bit 2). If
STRH<0> = 0 (REG08, bit 0) an interrupt will occur if
FIFOSTAT<2:0> = 0 or 7. If STRH<0> = 1 (REG08, bit 0) an
interrupt will occur if FIFOSTAT<2:0> = 0, 1, 6 or 7. The interrupt
can be read at REG01, bit 6 at the AD9736 IRQ pin.
To enter Auto mode, complete the preceding steps then set SAUTO
= 1 (REG09, bit 6). Next set the SYNC interrupt = 0 (REG01, bit 2),
to allow the phase offset (PHOF<1:0>) to be automatically updated
if FIFOSTAT<2:0> violates the threshold value.
The FIFOSTAT signal is filtered to improve noise immunity and
reduce unnecessary phase offset updates. The filter operates with
the following algorithm:
FIFOSTAT = FIFOSTAT + Delta FIFOSTAT / 2 ^ SFLT<3:0>
Where 0 <= SFLT<3:0> <= 12. Values greater than 12 are set to 12.
SAMPLE_HOLD
SAMPLE_SETUP
SAMPLE_DELAY
EXTERNAL_DELAY
INTERNAL_DELAY
B
C
D
E
F
G
H
I
J
K
M
O
L
N
P
R
Q
A
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
0
1
2
3
4
5
6
7
0
1
2
3
A
C
E
G
I
K
M
4
5
6
7
0
1
2
3
4
5
6
7
4
0
4
4
4
A
B
C
D
E
F
G
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I
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M
5
6
7
0
1
B
D
F
H
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1
2
3
4
DACCLK
DATACLK_OUT
DATACLK_IN
DATA_IN
CSS1
D1
CSS2
D2
WRITE_PTR1
M0
M1
M2
M3
M4
M5
M6
M7
READ_PTR1
FIFOSTAT
DAC_DATA
Figure 29. SYNC Logic Timing Diagram
Safe Zone
Error Zone
Data ‘A’ can be
safely read from
the FIFO in the
Safe Zone. In
the Error Zone,
the pointers
may briefly
overlap due to
clock jitter or
FIFOSTAT is set
equal to the
write pointer
each time the
read pointer
changes from 7
to 0.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD9736-EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9735 DAC, 10-/12-/14BIT, 1200 MSPS DACS - Bulk |
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| AD9737ABBCZ | 功能描述:IC DAC 11BIT 2.5GSPS RF 160BGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD9737ABBCZRL | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 11-Bit 2.5 GSPS RF RoHS:否 制造商:Analog Devices 轉(zhuǎn)換器數(shù)量:4 DAC 輸出端數(shù)量:4 轉(zhuǎn)換速率: 分辨率:12 bit 接口類型:Serial (I2C) 穩(wěn)定時間: 最大工作溫度:+ 105 C 安裝風格: 封裝 / 箱體:TSSOP 封裝:Reel |
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