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參數資料
| 型號： | AD9713BAP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 12-Bit, 100 MSPS D/A Converters |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.027 us SETTLING TIME, 12-BIT DAC, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數： | 5/12頁 |
| 文件大小： | 329K |
| 代理商： | AD9713BAP |
AD9712B/AD9713B
REV. B
–5–
DIE LAY OUT AND ME T ALIZAT ION INFORMAT ION
Die Dimensions . . . . . . . . . . . . . . . . . 220
×
196
×
15 (
±
2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
×
4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V
S
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
T HE ORY AND APPLICAT IONS
T he AD9712B and AD9713B high speed digital-to-analog
converters utilize Most Significant Bit (MSB) decoding and
segmentation techniques to reduce glitch impulse and main-
tain 12-bit linearity without trimming.
As shown in the functional block diagram, the design is based
on four main subsections: the Decoder/Driver circuits, the
T ransparent Latches, the Switch Network, and the Control Am-
plifier. An internal bandgap reference is also included to allow
operation with a minimum of external components.
Digital Inputs/T iming
T he AD9712B employs single-ended ECL-compatible inputs
for data inputs D
1
–D
12
and LAT CH ENABLE. T he internal
ECL midpoint reference is designed to match 10K ECL device
thresholds. On the AD9713B, a T T L translator is added at each
input; with this exception, the AD9712B and AD9713B are
identical.
In the Decoder/Driver section, the four MSBs (D
1
–D
4
) are
decoded to 15 “thermometer code” lines. An equalizing delay is
included for the eight Least Significant Bits (LSBs) and
LAT CH ENABLE. T his delay minimizes data skew, and data
setup and hold times at the latch inputs; this is important when
operating the latches in the transparent mode. Without the
delay, skew caused by the decoding circuits would degrade
glitch impulse.
T he latches operate in their transparent mode when LAT CH
ENABLE (Pin 26) is at logic level “0.” T he latches should be
used to synchronize data to the current switches by applying a
narrow LAT CH ENABLE pulse with proper data setup and
hold times as shown in the T iming Diagram. An external latch
at each data input, clocked out of phase with the Latch Enable,
operates the AD9712B/AD9713B in a master slave (edge-
triggered) mode. T his is the optimum way to operate the DAC
because data is always stable at the DAC input. An external
latch eases timing constraints when using the converter.
Although the AD9712B/AD9713B chip is designed to provide
isolation from digital inputs to the outputs, some coupling of
digital transitions is inevitable, especially with T T L or CMOS
inputs applied to the AD9713B. Digital feedthrough can be re-
duced by forming a low-pass filter using a (200
) series resistor
in series with the capacitance of each digital input; this rolls off
the slew rate of the digital inputs.
References
As shown in the functional block diagram, the internal bandgap
reference, control amplifier, and reference input are pinned out
for maximum user flexibility when setting the reference.
When using the internal reference, REFERENCE OUT (Pin 20)
should be connected to CONT ROL AMP IN (Pin 19). CON-
T ROL AMP OUT (Pin 18) should be connected to REFER-
ENCE IN (Pin 17) through a 20
resistor. A 0.1
μ
F ceramic
capacitor from Pin 17 to –V
S
(Pin 15) improves settling by
decoupling switching noise from the current sink base line. A
reference current cell provides feedback to the control amp by
sinking current through R
SET
(Pin 24).
t
S
– INPUT SETUP TIME
t
LPW
– LATCH PULSE WIDTH
– OUTPUT PROPAGATION DELAY
t
PD
t
H
– INPUT HOLD TIME
t
ST
– OUTPUT SETTLING TIME
OUTPUT
ERROR
ERROR
BAND
t
PD
LATCH
ENABLE
t
ST
t
LPW
t
S
t
H
VALID DATA
t
PD
DATA INPUTS
OUTPUT
LATCH ENABLE
Timing Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| AD9712 | 12-BIT, 100MSPS D/A CONVERTERS |
| AD9713BAN | REC3-SRW_DRW/H* Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 05V; Power: 3W; 2kV, 4kVDC & 6kVDC Isolation; Industry Standard 3W DIP24 Package; Feedback Regulated Output; Continuous Short Circuit Protection; Wide Input 2:1 & 4:1; Medical Approvals (4kV/6kV Versions); EN and UL Certificates; 3 Pinout Options, 3 Case Styles; Control Pin Option; Efficiency to 86% |
| AD9712JN | 12-BIT, 100MSPS D/A CONVERTERS |
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相關代理商/技術參數 |
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|---|---|
| AD9713BBN | 制造商:Rochester Electronics LLC 功能描述:12BIT TTL 80MSPS DAC IC - Bulk |
| AD9713BBP | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R 12-bit 28-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:12BIT TTL 80MSPS DAC IC - Bulk |
| AD9713BSE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12-Bit Digital-to-Analog Converter |
| AD9713BSE/883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 100 MSPS D/A Converters |
| AD9713BSQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12-Bit Digital-to-Analog Converter |
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