參數(shù)資料
型號： AD9709ASTZ
廠商： Analog Devices Inc
文件頁數(shù)： 9/32頁
文件大?。?/td> 0K
描述： IC DAC 8BIT DUAL 125MSPS 48-LQFP
產品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 1
系列： TxDAC+®
設置時間： 35ns
位數(shù)： 8
數(shù)據接口： 并聯(lián)
轉換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 450mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應商設備封裝： 48-LQFP（7x7）
包裝： 托盤
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 125M
產品目錄頁面： 785 (CN2011-ZH PDF)
配用： AD9709-EBZ-ND - BOARD EVAL FOR AD9709
AD9709
Rev. B | Page 17 of 32
Digital signal paths should be kept short, and run lengths should be
matched to avoid propagation delay mismatch. The insertion of
a low value (that is, 20 Ω to 100 Ω) resistor network between
the AD9709 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs that
contribute to digital feedthrough. For longer board traces and
high data update rates, stripline techniques with proper
impedance and termination resistors should be considered to
maintain “clean” digital inputs.
The external clock driver circuitry provides the AD9709 with a
low-jitter clock input meeting the minimum and maximum logic
levels while providing fast edges. Fast clock edges help minimize
jitter manifesting itself as phase noise on a reconstructed waveform.
Therefore, the clock input should be driven by the fastest logic
family suitable for the application.
Note that the clock input can also be driven via a sine wave, which
is centered around the digital threshold (that is, DVDDx/2) and
meets the minimum and maximum logic threshold. This typically
results in a slight degradation in the phase noise, which becomes
more noticeable at higher sampling rates and output frequencies.
In addition, at higher sampling rates, the 20% tolerance of the
digital logic threshold should be considered because it affects
the effective clock duty cycle and, subsequently, cut into the
required data setup and hold times.
Input Clock and Data Timing Relationship
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9709 is rising-edge triggered and
therefore exhibits SNR sensitivity when the data transition is
close to this edge. In general, the goal when applying the AD9709 is
to make the data transition close to the falling clock edge. This
becomes more important as the sample rate increases. Figure 32
shows the relationship of SNR to clock/data placement.
60
50
40
30
20
10
0
–4
–3
–2
–1
0
1
2
3
4
S
NR
(
d
Bc)
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE (ns)
00
60
6-
03
1
Figure 32. SNR vs. Clock Placement @ fOUT = 20 MHz and fCLK = 125 MSPS
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相關代理商/技術參數(shù)
參數(shù)描述
AD9709ASTZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:8-Bit, 125 MSPS, Dual TxDAC Digital-to-Analog Converter
AD9709ASTZKL1 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9709ASTZRL 功能描述:IC DAC 8BIT DUAL 125MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據采集 - 數(shù)模轉換器 系列:TxDAC+® 產品培訓模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標準包裝:91 系列:- 設置時間:4µs 位數(shù):10 數(shù)據接口:MICROWIRE?，串行，SPI? 轉換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應商設備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:*
AD9709ASTZRL1 制造商:AD 制造商全稱:Analog Devices 功能描述:8-Bit, 125 MSPS, Dual TxDAC Digital-to-Analog Converter
AD9709-EB 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:
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