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參數(shù)資料
| 型號： | AD9661AKR-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | Laser Diode Driver with Light Power Control |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 174K |
| 代理商： | AD9661AKR-REEL |
AD9661A
REV. 0
–6–
T o choose a value, the user will need to determine the amount
of time the loop will be in hold mode, t
HOLD
, the maximum
change in laser output power the application can tolerate, and
the laser efficiency (defined as the change in laser output power
to the change in laser diode current). As an example, if an ap-
plication requires 5 mW of laser power
±
5%, and the laser diode
efficiency is 0.25 mW/mA, then
I
MAX
=
5
mW
×
(5%)/ 0.25
mW
mA
=
1.0
mA
If the same application had a hold time requirement of 250
μ
s,
then the minimum value of the hold capacitor would be:
C
HOLD
=
18
×
10
±9
×
250
μ
s
1.0
mA
=
4.5
nF
When determining the calibration time, the T /H and the exter-
nal hold capacitor can be modeled using the simple RC circuit
illustrated below.
C
HOLD
R
AD9661A
T/H
TZA
POWER LEVEL
POWER MONITOR
HOLD
EXTERNAL HOLD
Figure 3. Circuitry Model for Determining Calibration Times
Using this model, the voltage at the hold capacitor is
V
CHOLD
=
V
t
=
0
+
(
V
t
=
∞
±
V
t
=
0
) 1±
e
±
t
τ
where t = 0 is when the calibration begins (
CAL
goes logic
LOW), V
t = 0
is the voltage on the hold cap at t = 0, V
t =
∞
is the
steady state voltage at the hold cap with the loop closed, and
τ
= R
CHOLD
is the time constant. With this model the error in
V
CHOLD
for a finite calibration time, as compared to V
t =
∞
, can
be estimated from the following table and chart:
T able II.
t
CALIBRAT ION
% Final Value
E rror %
7
τ
6
τ
5
τ
4
τ
3
τ
2
τ
τ
99.9
99.7
99.2
98.1
95.0
86.5
63.2
0.09
0.25
0.79
1.83
4.97
13.5
36.8
T he laser diode’s output power will then vary from 0 to P
LD MAX
for an input range of V
REF
to V
REF
+1.6 V @ the POWER
LEVEL input.
Minimum specifications for I
MONIT OR MAX
should be used when
choosing R
GAIN
. Users are cautioned that laser diode/photo
diode combinations that produce monitor currents that are less
than I
MONIT OR MAX
in the equation above will produce higher la-
ser output power than predicted, which may damage the laser
diode. Such a condition is possible if R
GAIN
is calculated using
typical instead of minimum monitor current specifications. In
that case the input range to the AD9661A POWER LEVEL
input should be limited to avoid damaging laser diodes.
Another approach would be to use a potentiometer for R
GAIN
.
T his allows users to optimize the value of R
GAIN
for each laser
diode/photo diode combination’s monitor current. T he draw-
back to this approach is that potentiometers’ stray inductance
and capacitance may cause the transimpedance amplifier to
overshoot and degrade its settling, and the value of C
GAIN
may
not be optimized for the entire potentiometer’s range.
C
GAIN
optimizes the response of the transimpedance amplifier
and should be chosen as from the table below. Choosing C
GAIN
larger than the recommended value will slow the response of the
amplifier. Lower values improve T ZA bandwidth but may cause
the amplifier to oscillate.
T able I.
Recommended
C
GAIN
R
GAIN
2.5 k
1.5 k
1 k
500
2 pF
3 pF
4 pF
8 pF
Choosing C
HOLD
Choosing values for the hold capacitor, C
HOLD
, is a tradeoff
between output current droop when the control loop is open,
and the time it takes to calibrate and recalibrate the laser power
when the loop is closed.
T he amount of output current droop is determined by the value
of the hold capacitor and the leakage current at that node.
When the control loop is open (
CAL
logic HIGH), the pin con-
nection for the hold capacitor (HOLD) is a high impedance in-
put. Leakage current will range from
±
200; this low current
minimizes the droop in the output power level. Assuming the
worst case current of
±
200 nA, the output current will change
as follows:
±
I
OUT
=
18
×
10
±9
C
HOLD
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