參數(shù)資料
型號: AD9648BCPZRL7-125
廠商: Analog Devices Inc
文件頁數(shù): 35/44頁
文件大小: 0K
描述: IC ADC 14BIT 125MSPS 64LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 14
采樣率(每秒): 125M
數(shù)據(jù)接口: LVDS,并聯(lián),串行,SPI
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,2 個差分
AD9648
Rev. 0 | Page 40 of 44
User I/O Control 2 (Register 0x101)
Bit 7—OEB Pin Enable
If the OEB pin enable bit (Bit 7) is set, the OEB pin is enabled.
If Bit 7 is clear, the OEB pin is disabled (default).
Bits[6:1]—Open
Bit 0—SDIO Pull-Down
Bit 0 can be set to disable the internal 30 kΩ pull-down on the
SDIO pin, which can be used to limit the loading when many
devices are connected to the SPI bus.
User I/O Control 3 (Register 0x102)
Bits[7:4]—Open
Bit 3—VCM Power-Down
Bit 3 can be set high to power down the internal VCM
generator. This feature is used when applying an external
reference.
Bits[2:0]—Open
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