參數(shù)資料
型號(hào): AD9644-80KITZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 19/44頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9644
設(shè)計(jì)資源: AD9644 Gerber Files
AD9644 80KITZ BOM
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 2
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行
輸入范圍: 1.4 ~ 2.1 Vpp
在以下條件下的電源(標(biāo)準(zhǔn)): *
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9644
已供物品:
AD9644
Data Sheet
Rev. C | Page 26 of 44
Table 10. AD9644 JESD204A Typical Configurations
AD9644 Configuration
JESK204A Link A Settings
JESD204A Link B Settings
Comments
M = 1; L = 1; S = 1; F = 2
Maximum sample rate = 80 MSPS or 155 MSPS
Two Converters
N’ = 16; CF = 0
Two JESD204A Links
CS = 0, 1, 2; K = N/A
One Lane Per Link
SCR = 0, 1; HD = 0
M = 2; L = 2; S = 1; F = 2
Disabled
Maximum sample rate = 80 MSPS or 155 MSPS
Two Converters
N’ = 16
Required for applications needing two aligned
samples (I/Q applications)
One JESD204A Link
CF = 0; CS = 0, 1, 2
Two Lanes Per Link
K = 16; SCR = 0, 1;
HD = 0
M = 2; L = 1; S = 1; F = 4
Disabled
Maximum sample rate = 80 MSPS
Two Converters
N’ = 16
One JESD204A Link
CF = 0; CS = 0, 1, 2
One Lane Per Link
K = 8; SCR = 0, 1; HD = 0
09180-
201
DATA
FROM
ADC
FRAME
ASSEMBLER
(ADD TAIL BITS)
OPTIONAL
SCRAMBLER
1 + x14 + x15
8B/10B
ENCODER
TO
RECEIVER
Figure 63. AD9644 ADC Output Data Path
09180-
200
WORD 0[13:6]
SYMBOL 0[9:0]
WORD 0[5:0],TAIL BITS[1:0]
SYMBOL 1[9:0]
WORD 1[13:6]
SYMBOL 2[9:0]
WORD 1[5:0], TAIL BITS[1:0]
SYMBOL 3[9:0]
TIME
FRAME 0
FRAME 1
Figure 64. AD9644 14-Bit Data Transmission with Tail Bits
09180-
202
8B/10B
DECODER
OPTIONAL
DESCRAMBLER
1 + x14 + x15
FRAME
ALIGNMENT
DATA
OUT
FROM
TRANSMITTER
Figure 65. Required Receiver Data Path
Initial Frame Synchronization
The serial interface must synchronize to the frame boundaries
before data can be properly decoded. The JESD204A standard
has a synchronization routine to identify the frame boundary.
When the DSYNC pin is taken low for at least two clock cycles,
the AD9644 enters the code group synchronization mode. The
AD9644 transmits the K28.5 comma symbol until the receiver
achieves synchronization. The receiver should then deassert the
sync signal (take DSYNC high) and the AD9644 begins the
initial lane alignment sequence (when enabled through Bits[3:2]
of Address 0x60) and subsequently begins transmitting sample
data. The first non-K28.5 symbol corresponds to the first octet
in a frame.
The DSYNC input can be driven either from a differential
LVDS source or by using a single-ended CMOS driver circuit.
The DSYNC input default to LVDS mode but can be set to
CMOS mode by setting Bit 4 in SPI Address 0x61. If it is driven
differentially from an LVDS source, then an external 100
termination resistor should be provided. If the DSYNC input is
driven single-ended then the CMOS signal should be connected
to the DSYNC+ signal and the DSYNC signal should be left
disconnected.
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