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參數(shù)資料
| 型號(hào)： | AD9644-80KITZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 18/44頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9644 |
| 設(shè)計(jì)資源： | AD9644 Gerber Files AD9644 80KITZ BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 1.4 ~ 2.1 Vpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | * |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9644 |
| 已供物品： | 板 |
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Data Sheet
AD9644
Rev. C | Page 25 of 44
Figure 62 shows a simplified block diagram of the AD9644
JESD204A links. The two links each have a primary and a
secondary converter input and lane output. By default, the
primary Input 0 of Link A is ADC Converter A and its primary
lane Output 0 is sent on output Lane A. The primary Input 0 of
Link B is ADC Converter B and its primary lane Output 0 is
sent on output Lane B. Muxes throughout the design are used to
enable secondary inputs/outputs and swap lane outputs for other
configurations. The JESD204A block for AD9644 is designed to
support the configurations described in Table 10 via a quick
configuration register at Address 0x5E accessible via the SPI bus.
In addition to the default mode, the user can program the AD9644
to output both ADC channels on a single lane (F = 4). This mode
allows use of a single high speed data lane, which simplifies board
layout and connector requirements. In Figure 64 the ADC A
output is represented by Word 0 and the ADC B output by Word 1.
The third output mode utilizes a single link to support both
channels. In single link mode, the DSYNCA pin is used to support
both outputs. This mode is useful for optimal alignment between
the output channels.
The 8B/10B encoding works by taking eight bits of data (an octet)
and encoding them into a 10-bit symbol. By default in the
AD9644, the 14-bit converter word is broken into two octets.
Bit 13 through Bit 6 are in the first octet. The second octet
contains Bit 5 through Bit 0 and two tail bits. The MSB of the tail
bits can also be used to indicate an out-of-range condition. The
tail bits are configured using the JESD204A link control
Register 1, Address 0x60, Bit 6.
The two resulting octets are optionally scrambled and encoded
into their corresponding 10-bit code. The scrambling function
is controlled by the JESD204A scrambling and lane configuration
register, Address 0x06E, Bit 7. Figure 63 shows how the 14-bit
data is taken from the ADC, the tail bits are added, the two octets
are scrambled, and how the octets are encoded into two 10-bit
symbols. Figure 63 illustrates the default data format.
The scrambler uses a self-synchronizing polynomial-based
algorithm defined by the equation 1 + x14 + x15. The descrambler
in the receiver should be a self-synchronizing version of the
scrambler polynomial. Figure 65 shows the corresponding
receiver data path.
Refer to JEDEC Standard No. 204A-April 2008, Section 5.1, for
complete transport layer and data format details and Section 5.2
for a complete explanation of scrambling and descrambling.
AD9644
DUAL ADC
JESD204A LINK A
(M = 0, 1, 2; L = 0, 1, 2)
CONVERTER A
SAMPLE
PRIMARY
CONVERTER
INPUT [0]
PRIMARY
LANE
OUTPUT [0]
SECONDARY
CONVERTER
INPUT [1]
SECONDARY
LANE
OUTPUT [1]
JESD204A LINK B
(M = 0, 1, 2; L = 0, 1, 2)
SECONDARY
CONVERTER
INPUT [1]
SECONDARY
LANE
OUTPUT [1]
PRIMARY
CONVERTER
INPUT [0]
PRIMARY
LANE
OUTPUT [0]
CONVERTER B
SAMPLE
A
B
A
B
CONVERTER B
INPUT
CONVERTER A
INPUT
LANE B
LANE A
LANE 0
LANE 1
LINK A
~SYNC
LINK B
~SYNC
LANE
MUX
(SPI
REGISTER
0x5F)
LANE 1
LANE 0
CONVERTER A
CONVERTER B
09180-
045
Figure 62. AD9644 Transmit Link Simplified Block Diagram
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