參數(shù)資料
型號(hào)： AD9600ABCPZ-105
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/72頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT 105MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 10
采樣率（每秒）： 105M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 650mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸入數(shù)目和類型： 4 個(gè)單端，單極；2 個(gè)差分，單極
AD9600
Rev. B | Page 29 of 72
Table 12. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin
SCLK/DFS
SDIO/DCS
AGND
Offset binary (default)
DCS disabled
AVDD
Twos complement
DCS enabled (default)
Digital Output Enable Function (OEB)
The AD9600 has a flexible three-state ability for the digital
output pins. The three-state mode can be enabled by using the
SMI SDO/OEB pin or the SPI interface. If the SMI SDO/OEB pin
is low, the output data drivers are enabled. If the SMI SDO/OEB pin
is high, the output data drivers are placed into a high impedance
state. This output enable function is not intended for rapid access
to the data bus. Note that OEB is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply voltage.
When the device uses the SPI interface, each channel’s data and
fast detect output pins can be independently three-stated by
using the output enable bar bit in Register 0x14.
TIMING
The AD9600 provides latched data with a pipeline delay of
12 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
The length of the output data lines and the loads placed on them
should be minimized to reduce transients within the AD9600.
These transients can degrade the dynamic performance of the
converter. The lowest typical conversion rate of the AD9600 is
typically 10 MSPS. At clock rates below 10 MSPS, dynamic
performance may degrade.
Data Clock Output (DCO)
The AD9600 provides two data clock output (DCO) signals
intended for capturing the data in an external register. The data
outputs are valid on the rising edge of DCO, unless the polarity
has been changed via the SPI. See the timing diagrams shown
in Figure 2 and Figure 3 for more information.
Table 13. Output Data Format
Input (V)
Condition (V)
Binary Output Mode
Twos Complement Mode
Overrange
(VIN+ ) (VIN )
< VREF 0.5 LSB
00 0000 0000
10 0000 0000
1
(VIN+ ) (VIN )
= –VREF
00 0000 0000
10 0000 0000
0
(VIN+ ) (VIN )
= 0
10 0000 0000
00 0000 0000
0
(VIN+ ) (VIN )
= +VREF 1.0 LSB
11 1111 1111
01 1111 1111
0
(VIN+ ) (VIN )
> +VREF 0.5 LSB
11 1111 1111
01 1111 1111
1
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參數(shù)描述
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AD9600ABCPZ-150 功能描述:IC ADC 10BIT 150MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
AD9600BCPZ-105 制造商:Analog Devices 功能描述:ADC Dual Pipelined 105Msps 10-bit Parallel/LVDS 64-Pin LFCSP EP
AD9600BCPZ-125 制造商:Analog Devices 功能描述:ADC Dual Pipelined 125Msps 10-bit Parallel/LVDS 64-Pin LFCSP EP
AD9600BCPZ-150 制造商:Analog Devices 功能描述:
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