Typical (typ) is given for VS
參數(shù)資料
型號(hào): AD9572ACPZPEC-RL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 14/20頁(yè)
文件大小: 0K
描述: IC PLL CLOCK GEN 25MHZ 40LFCSP
標(biāo)準(zhǔn)包裝: 2,500
類(lèi)型: 時(shí)鐘發(fā)生器,扇出配送,多路復(fù)用器
PLL:
輸入: 晶體
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:7
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 156.25MHz
除法器/乘法器: 是/無(wú)
電源電壓: 2.97 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 40-LFCSP-WQ(6x6)
包裝: 帶卷 (TR)
AD9572
Rev. B | Page 3 of 20
SPECIFICATIONS
PLL CHARACTERISTICS
Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PHASE NOISE CHARACTERISTICS
PLL Noise (106.25 MHz LVDS Output)
At 1 kHz
123
dBc/Hz
33.33 MHz output disabled
At 10 kHz
127
dBc/Hz
33.33 MHz output disabled
At 100 kHz
129
dBc/Hz
33.33 MHz output disabled
At 1 MHz
150
dBc/Hz
33.33 MHz output disabled
At 10 MHz
152
dBc/Hz
33.33 MHz output disabled
At 30 MHz
153
dBc/Hz
33.33 MHz output disabled
PLL Noise (156.25 MHz LVDS Output)
At 1 kHz
118
dBc/Hz
33.33 MHz output disabled
At 10 kHz
125
dBc/Hz
33.33 MHz output disabled
At 100 kHz
126
dBc/Hz
33.33 MHz output disabled
At 1 MHz
145
dBc/Hz
33.33 MHz output disabled
At 10 MHz
151
dBc/Hz
33.33 MHz output disabled
At 30 MHz
151
dBc/Hz
33.33 MHz output disabled
PLL Noise (125 MHz LVDS Output)
At 1 kHz
119
dBc/Hz
33.33 MHz output disabled
At 10 kHz
127
dBc/Hz
33.33 MHz output disabled
At 100 kHz
128
dBc/Hz
33.33 MHz output disabled
At 1 MHz
147
dBc/Hz
33.33 MHz output disabled
At 10 MHz
151
dBc/Hz
33.33 MHz output disabled
At 30 MHz
152
dBc/Hz
33.33 MHz output disabled
PLL Noise (100 MHz LVDS Output)
At 1 kHz
121
dBc/Hz
33.33 MHz output disabled
At 10 kHz
128
dBc/Hz
33.33 MHz output disabled
At 100 kHz
130
dBc/Hz
33.33 MHz output disabled
At 1 MHz
147
dBc/Hz
33.33 MHz output disabled
At 10 MHz
150
dBc/Hz
33.33 MHz output disabled
At 30 MHz
150
dBc/Hz
33.33 MHz output disabled
PLL Noise (106.25 MHz LVPECL Output)
At 1 kHz
121
dBc/Hz
33.33 MHz output disabled
At 10 kHz
128
dBc/Hz
33.33 MHz output disabled
At 100 kHz
129
dBc/Hz
33.33 MHz output disabled
At 1 MHz
151
dBc/Hz
33.33 MHz output disabled
At 10 MHz
154
dBc/Hz
33.33 MHz output disabled
At 30 MHz
155
dBc/Hz
33.33 MHz output disabled
PLL Noise (156.25 MHz LVPECL Output)
At 1 kHz
119
dBc/Hz
33.33 MHz output disabled
At 10 kHz
125
dBc/Hz
33.33 MHz output disabled
At 100 kHz
126
dBc/Hz
33.33 MHz output disabled
At 1 MHz
147
dBc/Hz
33.33 MHz output disabled
At 10 MHz
152
dBc/Hz
33.33 MHz output disabled
At 30 MHz
153
dBc/Hz
33.33 MHz output disabled
相關(guān)PDF資料
PDF描述
VE-BTN-MV-S CONVERTER MOD DC/DC 18.5V 150W
X9410WP24I-2.7 IC XDCP DUAL 64-TAP 10K 24-DIP
X9410WP24I IC XDCP DUAL 64-TAP 10K 24-DIP
D38999/20JD15JD CONN RCPT 15POS WALL MNT W/SCKT
AD9571ACPZPEC-RL IC PLL CLOCK GEN 25MHZ 40LFCSP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9572-EVALZ-LVD 制造商:AD 制造商全稱:Analog Devices 功能描述:Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs
AD9572-EVALZ-PEC 制造商:AD 制造商全稱:Analog Devices 功能描述:Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs
AD9572XCPZLVD 制造商:Analog Devices 功能描述:
AD9572XCPZPEC 制造商:Analog Devices 功能描述:
AD9573 制造商:AD 制造商全稱:Analog Devices 功能描述:PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs