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參數(shù)資料
| 型號： | AD9557BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK XLATR PLL 1250MHZ 40LFCSP |
| 產(chǎn)品變化通告： | Minor Mask Change 11/Apr/2012 |
| 標準包裝： | 750 |
| 類型： | 時鐘/頻率轉(zhuǎn)換器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.25GHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD9557
Rev. B | Page 37 of 92
STATUS AND CONTROL
MULTIFUNCTION PINS (M3 TO M0)
The AD9557 has four digital CMOS I/O pins (M3 to M0) that are
configurable for a variety of uses. To use these functions, the user
must enable them by writing a 0x01 to Register 0x0200. The
function of these pins is programmable via the register map. Each
pin can control or monitor an assortment of internal functions,
based on the contents of Register 0x0201 to Register 0x0204.
To monitor an internal function with a multifunction pin, write
a Logic 1 to the most significant bit of the register associated
with the desired multifunction pin. The value of the seven least
significant bits of the register defines the control function, as shown
To control an internal function with a multifunction pin, write a
Logic 0 to the most significant bit of the register associated with
the desired multifunction pin. The monitored function depends
on the value of the seven least significant bits of the register, as
shown in Table 125.
If more than one multifunction pin operates on the same control
signal, then internal priority logic ensures that only one multi-
function pin serves as the signal source. The selected pin is the
one with the lowest numeric suffix. For example, if both M0 and
M3 operate on the same control signal, M0 is used as the signal
source and the redundant pins are ignored.
At power-up, the multifunction pins can force the device into
certain configurations, as defined in the initial pin programming
section. This functionality, however, is valid only during power-
up or following a reset, after which the pins can be reconfigured
via the serial programming port or via the EEPROM.
If the output SYNC function is to be controlled using an M pin,
1. First, enable the M pins by writing Register 0x0200 = 0x01.
2. Issue an I/O update (Register 0x0005 = 0x01).
3. Set the appropriate M pin function.
If this process is not followed, a SYNC pulse is issued automatically.
IRQ PIN
The AD9557 has a dedicated interrupt request (IRQ) pin. Bits[1:0]
of the IRQ pin output mode register (Register 0x0209) control
how the IRQ pin asserts an interrupt, based on the value of the
two bits, as follows:
00—The IRQ pin is high impedance when deasserted and active
low when asserted and requires an external pull-up resistor.
01—The IRQ pin is high impedance when deasserted and active
high when asserted and requires an external pull-down
resistor.
10—The IRQ pin is Logic 0 when deasserted and Logic 1 when
asserted.
11—The IRQ pin is Logic 1 when deasserted and Logic 0 when
asserted. (This is the default operating mode.)
The AD9557 asserts the IRQ pin when any bit in the IRQ monitor
register (Address 0x0D02 to Address 0x0D07) is a Logic 1. Each
bit in this register is associated with an internal function that is
capable of producing an interrupt. Furthermore, each bit of the
IRQ monitor register is the result of a logical AND of the associated
internal interrupt signal and the corresponding bit in the IRQ mask
register (Address 0x020A to Address 0x020E). That is, the bits in
the IRQ mask register have a one-to-one correspondence with
the bits in the IRQ monitor register. When an internal function
produces an interrupt signal and the associated IRQ mask bit is
set, then the corresponding bit in the IRQ monitor register is set.
The user should be aware that clearing a bit in the IRQ mask
register removes only the mask associated with the internal
interrupt signal. It does not clear the corresponding bit in the
IRQ monitor register.
The IRQ pin is the result of a logical OR of all the IRQ monitor
register bits. Thus, the AD9557 asserts the IRQ pin as long as
any IRQ monitor register bit is a Logic 1. Note that it is possible
to have multiple bits set in the IRQ monitor register. Therefore,
when the AD9557 asserts the IRQ pin, it may indicate an interrupt
from several different internal functions. The IRQ monitor register
provides the user with a means to interrogate the AD9557 to
determine which internal function produced the interrupt.
Typically, when the IRQ pin is asserted, the user interrogates
the IRQ monitor register to identify the source of the interrupt
request. After servicing an indicated interrupt, the user should
clear the associated IRQ monitor register bit via the IRQ clearing
register (Address 0x0A04 to Address 0x0A09). The bits in the IRQ
clearing register have a one-to-one correspondence with the bits in
the IRQ monitor register. Note that the IRQ clearing register is
autoclearing. The IRQ pin remains asserted until the user clears
all of the bits in the IRQ monitor register that indicate an interrupt.
It is also possible to collectively clear all of the IRQ monitor register
bits by setting the clear all IRQs bit in the reset function register
(Register 0x0A03, Bit 1). Note that this is an autoclearing bit.
Setting this bit results in deassertion of the IRQ pin. Alternatively,
the user can program any of the multifunction pins to clear all
IRQs. This allows the user to clear all IRQs by means of a hardware
pin rather than by using a serial I/O port operation.
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