參數(shù)資料
型號: AD9553BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 12/44頁
文件大?。?/td> 0K
描述: IC INTEGER-N CLCK GEN 32LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘/頻率轉(zhuǎn)換器
PLL:
主要目的: 以太網(wǎng),GPON,SONET/SHD,T1/E1
輸入: CMOS,LVDS,晶體
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP(5x5)
包裝: 托盤
配用: AD9553/PCBZ-ND - BOARD EVAL FOR AD9553
AD9553
Rev. A | Page 2 of 44
TABLE OF CONTENTS
REVISION HISTORY
10/10—Rev. 0 to Rev. A
Changes to Features Section, Applications Section, and General
Description Section.......................................................................... 1
Added Table Summary to Specifications Section......................... 3
Added Supply Voltage Parameter, Table 1..................................... 3
Changes to Table 5............................................................................ 4
Changes to Table 6 and Crystal Load Capacitance Parameter,
Table 7 ................................................................................................ 5
Changes to Table 8............................................................................ 6
Changes to Table 9............................................................................ 7
Changes to Pin 1 and Pin 15, Table 13......................................... 10
Added Figure 4, Renumbered Sequentially ................................ 11
Added Figure 10, Figure 12, Figure 13, and Figure 14............... 12
Added Input/Output Termination Recommendations Section,
Figure 25, Figure 26, and Figure 27.............................................. 15
Moved Theory of Operation and Figure 28................................ 16
Changed General Description Section to Overview Section and
Moved............................................................................................... 16
Changes to Overview Section ....................................................... 16
Changes to Preset Frequencies Section and Table 14 ................ 17
Changes to Table 15........................................................................ 18
Changes to Table 16 ....................................................................... 19
Changes to PLL (PFD, Charge Pump, VCO, Feedback Divider
Section.............................................................................................. 22
Changes to Loop Filter Section, Figure 31, Table 17, PLL Locked
Indicator Section, and Output Dividers Section........................ 23
Changes to Output Driver Mode Control Section..................... 24
Changes to Output Driver Polarity (CMOS) Section................ 25
Changes to Output/Input Frequency Relationship Section...... 26
Changes to Calculating Divider Values Section......................... 27
Changes to Automatic Power-On Reset Section........................ 28
Changes to Thermal Performance Section ................................. 29
Changes to Address 0x18, Address 0x32, and Address 0x34,
Table 27 ............................................................................................ 33
Changes to Address 0x18, Table 31.............................................. 37
Change to Address 0x20, Table 34 ............................................... 38
Changes to Address 0x24, Table 35 and Address 0x28, Table 36 ...39
Changes to Address 0x32, Table 37.............................................. 40
Changes to Address 0x34, Table 39.............................................. 41
4/10—Revision 0: Initial Version
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