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參數資料
| 型號： | AD9548BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 60/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| 產品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 標準包裝： | 400 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD9548
Rev. E | Page 51 of 112
SERIAL CONTROL PORT
M7
M0
M1
M2
M3
M4
M5
M6
13-BIT ADDRESS
SPACE
READ ONLY
REGION
READ/WRITE
REGION
ANALOG BLOCKS AND
DIGITAL CORE
POWER-ON RESET
SERIAL CONTROL ARBITER
SPI
I
2
C
EEPROM
CONTROLLER
400kHz
MULTI-
FUNCTION
PIN CONTROL
LOGIC
SCLK/SCL
CS/SDA
SDIO
SDO
EEPROM
0
80
22
-0
26
Figure 52. Serial Port Functional Diagram
The AD9548 serial control port is a flexible, synchronous serial
communications port that provides a convenient interface to
many industry-standard microcontrollers and microprocessors.
The AD9548 serial control port is compatible with most
synchronous transfer formats, including Philips I2C, Motorola
SPI, and Intel SSR protocols. The serial control port allows
read/write access to the AD9548 register map.
In SPI mode, single or multiple byte transfers are supported. The
SPI port configuration is programmable via Register 0x0000. This
register is integrated into the SPI control logic rather than in the
register map and is distinct from the I2C Register 0x0000. It is also
inaccessible to the EEPROM controller.
A functional diagram of the serial control port, including its
relationship to the EEPROM, appears in Figure 52.
protocols, only one is active following power-up (as determined
by the multifunction pins, M0 to M2, during the startup
sequence). That is, the only way to change the serial port
protocol is to reset the device (or cycle the device power
supply). Both protocols use a common set of control pins as
shown in Figure 53.
AD9548
SCLK/SCL
CSB/SDA
SDO
SDIO
2
5
4
3
SERIAL
CONTROL
PORT
08
02
2-
02
7
Figure 53. Serial Control Port
SPI/IC PORT SELECTION
Because the AD9548 supports both SPI and I2C protocols, the
active serial port protocol depends on the logic state of the three
multifunction pins, M0 to M2, at startup. If all three pins are set
to Logic 0 at startup, then the SPI protocol is active. Otherwise,
the I2C protocol is active with seven different I2C slave address
settings based on the startup logic pattern on the M0 to M2 pins
(see Table 29). Note that the four MSBs of the slave address are
hardware coded as 1011.
Table 29. Serial Port Mode Selection
M2
M1
M0
Serial Port Mode
0
SPI
0
1
IC (address = 1001001)
0
1
0
IC (address = 1001010)
0
1
IC (address = 1001011)
1
0
IC (address = 1001100)
1
0
1
IC (address = 1001101)
1
0
IC (address = 1001110)
1
IC (address = 1001111)
SPI SERIAL PORT OPERATION
Pin Descriptions
The SCLK (serial clock) pin serves as the serial shift clock. This
pin is an input. SCLK synchronizes serial control port read and
write operations. The rising edge SCLK registers write data bits,
and the falling edge registers read data bits. The SCLK pin
supports a maximum clock rate of 40 MHz.
The SDIO (serial data input/output) pin is a dual-purpose pin
and acts as either an input only (unidirectional mode) or as
both an input and an output (bidirectional mode). The AD9548
default SPI mode is bidirectional.
The SDO (serial data output) pin is useful only in
unidirectional I/O mode. It serves as the data output pin for
read operations.
The CS (chip select) pin is an active low control that gates read
and write operations. This pin is internally connected to a 30 kΩ
pull-up resistor. When CS is high, the SDO and SDIO pins go
into a high impedance state.
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