參數(shù)資料
型號(hào)： AD9522-5/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 39/76頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9522-5
設(shè)計(jì)資源： AD9522 Eval Board Schematic
AD9522 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9522-5
主要屬性： 12 LVDS/24 CMOS 輸出
次要屬性： I²C & SPI 接口
已供物品： 板
AD9522-5
Rev. 0 | Page 44 of 76
PLL Power-Down
The PLL section of the AD9522 can be selectively powered
down. There are two PLL power-down modes set by
Register 0x010[1:0]: asynchronous and synchronous.
In asynchronous power-down mode, the device powers down as
soon as the registers are updated. In synchronous power-down
mode, the PLL power-down is gated by the charge pump to
prevent unwanted frequency jumps. The device goes into power-
down on the occurrence of the next charge pump event after the
registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing
0x230[1] = 1b, which turns off the bias to the distribution
section. If the LVDS power-down mode is normal operation
(0b), it is possible for a low impedance load on that LVDS
output to draw significant current during this power-down. If
the LVDS power-down mode is set to 1b, the LVDS output is
not protected from reverse bias and can be damaged under
certain termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs can be put into power-
down mode by individually writing to the appropriate registers.
The register map details the individual power-down settings for
each output. These settings are found in Register 0x0F0[0] to
Register 0x0FB[0].
Individual Clock Channel Power-Down
Any of the clock distribution channels can be powered down
individually by writing to the appropriate registers. Powering
down a clock channel is similar to powering down an individual
driver, but it saves more power because the dividers are also
powered down. Powering down a clock channel also automatically
powers down the drivers connected to it. The register map
details the individual power-down settings for each output
channel. These settings are found in 0x192[2], 0x195[2],
0x198[2], and 0x19B[2].
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