- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16534 > AD9522-3/PCBZ (Analog Devices Inc)BOARD EVAL FOR AD9522-3 CLK GEN PDF資料下載
參數(shù)資料
| 型號： | AD9522-3/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 63/84頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9522-3 CLK GEN |
| 設(shè)計(jì)資源： | AD9522 Eval Board Schematic AD9522 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9522-3 |
| 主要屬性： | 12 LVDS/24 CMOS 輸出，2 GHz VCO |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 板 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁當(dāng)前第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
AD9522-3
Rev. 0 | Page 66 of 84
REGISTER MAP DESCRIPTIONS
Table 49 through Table 59 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal
address. Reference to a specific bit or range of bits within a register is indicated by squared brackets. For example, [3] refers to Bit 3 and
[5:2] refers to the range of bits from Bit 5 through Bit 2.
Table 49. SPI Mode Serial Port Configuration
Reg Addr (Hex)
Bit(s)
Name
Description
000
[7]
SDO active
Selects unidirectional or bidirectional data transfer mode.
[7] = 0; SDIO pin used for write and read; SDO is high impedance (default).
[7] = 1; SDO used for read; SDIO used for write; unidirectional mode.
000
[6]
LSB first/addr incr
SPI MSB or LSB data orientation. (This register is ignored in I2C mode.)
[6] = 0; data-oriented MSB first; addressing decrements (default).
[6] = 1; data-oriented LSB first; addressing increments.
000
[5]
Soft reset
Soft reset.
[5] = 1 (self-clearing). Soft reset; restores default values to internal registers. This bit
self clears on the next SCLK cycle after the completion of writing to this register.
000
[4]
Unused
000
[3:0]
Mirror[7:4]
Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part
is in MSB or LSB first mode (see Register 0x000[6]). Set bits as follows:
[0] = [7]
[1] = [6]
[2] = [5]
[3] = [4]
004
[0]
Readback active registers
Select register bank used for a readback.
[0] = 0; read back buffer registers (default).
[0] = 1; read back active registers.
Table 50. I2C Mode Serial Port Configuration
Reg Addr (Hex)
Bit(s)
Name
Description
000
[7:6]
Unused
000
[5]
Soft reset
Soft reset.
[5] = 1 (self-clearing). Soft reset; restores default values to internal registers. This bit
self clears on the next SCL cycle after the completion of writing to this register.
000
[4]
Unused
000
[3:0]
Mirror[7:4]
Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part is
in MSB or LSB first mode (see Register 0x000[6]). Set bits as follows:
[0] = [7]
[1] = [6]
[2] = [5]
[3] = [4]
004
[0]
Readback active registers
Select register bank used for a readback.
[0] = 0; read back buffer registers (default).
[0] = 1; read back active registers.
Table 51. EEPROM ID
Reg Addr (Hex)
Bit(s)
Name
Description
005
[7:0]
EEPROM customer
version ID (LSB)
16-bit EEPROM ID[7:0]. This register, along with 0x006, allows the user to store a
unique ID to identify which version of the AD9522 register settings is stored in the
EEPROM. It does not affect AD9522 operation in any way (default: 0x00).
006
[7:0]
EEPROM customer
version ID (MSB)
16-bit EEPROM ID[15:8]. This register, along with 0x005, allows the user to store a
unique ID to identify which version of the AD9522 register settings is stored in the
EEPROM. It does not affect AD9522 operation in any way (default: 0x00).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FCBP110LD1L03S | KIT 3M LASERWIRE SFP+ |
| VE-J4D-EZ-S | CONVERTER MOD DC/DC 85V 25W |
| AD9520-2/PCBZ | BOARD EVAL AD9520-2 |
| AD9516-5/PCBZ | BOARD EVAL FOR AD9516-5 2.5GHZ |
| FCBP110LD1L05 | CABLE 10.5GBPS 5M LASERWIRE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9522-4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVDS/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO |
| AD9522-4/PCBZ | 功能描述:BOARD EVAL FOR AD9522-4 CLK GEN RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9522-4BCPZ | 功能描述:IC CLOCK GEN 1.6GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9522-4BCPZ-REEL7 | 功能描述:IC CLOCK GEN 1.6GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9522-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVDS/24 CMOS Output Clock Generator |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。