參數(shù)資料
型號(hào)： AD9520-4/PCBZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 70/80頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9520-4
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
AD9520 Eval Brd Schematic
AD9520 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9520-4
主要屬性： 1.4 ~ 1.8 GHz 輸出頻率
次要屬性： 接受 CMOS、LVDS 或者最高 250 MHz 的 LVPECL 基準(zhǔn)
已供物品： 板
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD9520-4BCPZ-REEL7-ND - IC CLOCK GEN 1.6GHZ VCO 64LFCSP
AD9520-4BCPZ-ND - IC CLOCK GEN 1.6GHZ VCO 64LFCSP
AD9520-4
Data Sheet
Rev. A | Page 72 of 80
Table 56. LVPECL Channel Dividers
Reg.
Addr.
(Hex) Bits
Name
Description
0x190 [7:4]
Divider 0 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays low.
A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x7).
[3:0]
Divider 0 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays high.
A value of 0x7 means that the divider is high for eight input clock cycles (default: 0x7).
0x191 7
Divider 0 bypass
Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
6
Divider 0 ignore SYNC
Ignores SYNC.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5
Divider 0 force high
Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that this bit
has no effect if the channel divider is bypassed, but the driver polarity can still be reversed.
0: divider output is forced to low (default).
1: divider output is forced to the setting stored in Bit 4 of this register.
4
Divider 0 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0]
Divider 0 phase offset
Phase offset (default: 0x0).
0x192 [7:3]
Unused
Unused.
2
Channel 0 power-down
Channel 0 powers down.
0: normal operation (default).
1: powered down. (Setting this bit puts OUT0/OUT0, OUT1/OUT1, and OUT2/OUT2 into safe power-
down mode.)
1
Channel 0 direct to output
Connects OUT0, OUT1, and OUT2 to Divider 0 or directly to VCO or CLK.
0: OUT0, OUT1, and OUT2 are connected to Divider 0 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0, OUT1, and OUT2.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0, OUT1, and OUT2.
If Register 0x1E1[1:0] = 01b, there is no effect.
0
Disable Divider 0 DCC
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x193 [7:4]
Divider 1 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays low.
A value of 0x3 means that the divider is low for four input clock cycles (default: 0x3).
[3:0]
Divider 1 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays high.
A value of 0x3 means that the divider is high for four input clock cycles (default: 0x3).
0x194 7
Divider 1 bypass
Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
6
Divider 1 ignore SYNC
Ignores SYNC.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5
Divider 1 force high
Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that this bit
has no effect if the channel divider is bypassed, but the driver polarity can still be reversed.
0: divider output is forced to low (default).
1: divider output is forced to the setting stored in Bit 4 of this register.
4
Divider 1 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0]
Divider 1 phase offset
Phase offset (default: 0x0).
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