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參數(shù)資料
| 型號： | AD9514BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIST 3OUT PLL 32LFCSP |
| 標準包裝： | 1,500 |
| 類型： | 扇出緩沖器（分配），除法器 |
| PLL： | 無 |
| 輸入： | 時鐘 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.6GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9514/PCBZ-ND - BOARD EVAL CLOCK 3CH AD9514 |
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AD9514
Rev. 0 | Page 18 of 28
FUNCTIONAL DESCRIPTION
OVERALL
The AD9514 provides for the distribution of its input clock
on up to three outputs simultaneously. OUT0 and OUT1 are
LVPECL levels. OUT2 can be set to either LVDS or CMOS
levels. Each output has its own divider that can be set for a
divide ratio selected from a list of integer values from 1
(bypassed) to 32.
OUT2 includes an analog delay block that can be set to add an
additional delay of 1.5 ns, 5 ns, or 10 ns full scale, each with
16 levels of fine adjustment.
CLK, CLKB—DIFFERENTIAL CLOCK INPUT
The CLK and CLKB pins are differential clock input pins.
This input works up to 1600 MHz. The jitter performance is
degraded by a slew rate below 1 V/ns. The input level should be
between approximately 150 mV p-p to no more than 2 V p-p.
Anything greater can result in turning on the protection diodes
on the input pins.
See Figure 23 for the CLK equivalent input circuit. This input
is fully differential and self-biased. The signal should be ac-
coupled using capacitors. If a single-ended input must be used,
this can be accommodated by ac coupling to one side of the
differential input only. The other side of the input should be
bypassed to a quiet ac ground by a capacitor.
2.5k
Ω
5k
Ω
5k
Ω
2.5k
Ω
CLKB
CLK
VS
CLOCK INPUT
STAGE
05596-
021
Figure 23 Clock Input Equivalent Circuit
SYNCHRONIZATION
Power-On SYNC
A power-on sync (POS) is issued when the VS power supply is
turned on to ensure that the outputs start in synchronization.
The power-on sync works only if the VS power supply transi-
tions the region from 2.2 V to 3.1 V within 35 ms. The POS can
occur up to 65 ms after VS crosses 2.2 V. Only outputs which are
not divide = 1 are synchronized.
05596-094
CLK
OUT
0V
3.3V
2.2V
3.1V
VS
CLOCK FREQUENCY
IS EXAMPLE ONLY
DIVIDE = 2
PHASE = 0
< 65ms
INTERNAL SYNC NODE
35ms
MAX
Figure 24. Power-On Sync Timing
SYNCB
If the setup configuration of the AD9514 is changed during
operation, the outputs can become unsynchronized. The
outputs can be re-synchronized to each other at any time.
Synchronization occurs when the SYNCB pin is pulled low and
released. The clock outputs (except where divide = 1) are forced
into a fixed state (determined by the divide and phase settings)
and held there in a static condition until the SYNCB pin is
returned to high. Upon release of the SYNCB pin, after four
cycles of the clock signal at CLK, all outputs continue clocking
in synchronicity (except where divide = 1).
When divide = 1 for an output, that output is not affected by
SYNCB.
05596-
093
CLK
SYNCB
OUT
3 CLK CYCLES
4 CLK CYCLES
EXAMPLE: DIVIDE
≥ 8
PHASE = 0
EXAMPLE DIVIDE
RATIO PHASE = 0
Figure 25. SYNCB Timing with Clock Present
05596-
092
4 CLK CYCLES
CLK
OUT
SYNCB
DEPENDS ON PREVIOUS STATE AND DIVIDE RATIO
§§
§
DEPENDS ON PREVIOUS STATE
EXAMPLE DIVIDE
RATIO PHASE = 0
MIN 5ns
Figure 26. SYNCB Timing with No Clock Present
The outputs of the AD9514 can be synchronized by using the
SYNCB pin. Synchronization aligns the phases of the clock
outputs, respecting any phase offset that has been set on a
particular output’s divider.
SYNCB
05596-
022
Figure 27. SYNCB Equivalent Input Circuit
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