參數(shù)資料
型號: AD9444BSVZ-80
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 14-Bit, 80 MSPS, A/D Converter
中文描述: 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100
封裝: LEAD FREE, PLASTIC, MS-026-AED, TQFP-100
文件頁數(shù): 6/40頁
文件大?。?/td> 1291K
代理商: AD9444BSVZ-80
AD9444
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
Rev. 0 | Page 6 of 40
AD9444BSVZ-80
Min
Typ
80
12.5
4
4
3
5.25
3
5
12
0.2
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High
1
(t
CLKH
)
CLK Pulse Width Low
1
(t
CLKL
)
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (t
PD
)
2
(DX, DCO+)
Output Propagation Delay—LVDS (t
PD
)
3
(DX+, DCO+)
Pipeline Delay (Latency)
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter, t
J
)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
VI
V
V
V
V
IV
VI
V
V
V
Max
10
8
7.5
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
Cycles
ns
ps rms
1
With duty cycle stabilizer (DCS) enabled.
2
Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load.
3
LVDS R
TERM
= 100 . Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
N–12
N–11
N
N+1
A
IN
CLK+
CLK–
DATA OUT
DCO+
DCO–
N
N+1
N–1
t
CLKH
t
CLKL
1/
f
S
t
PD
12 CLOCK CYCLES
t
CPD
0
Figure 2. LVDS Mode Timing Diagram
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