VDD = 3.3 V, V
參數(shù)資料
型號(hào): AD9433BSVZ-105
廠商: Analog Devices Inc
文件頁數(shù): 16/20頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 105MSPS 52TQFP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 105M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.43W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 52-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 52-TQFP-EP(10x10)
包裝: 托盤
輸入數(shù)目和類型: 2 個(gè)單端,單極;2 個(gè)差分,單極
AD9433
Rev. A | Page 5 of 20
SWITCHING SPECIFICATIONS
VDD = 3.3 V, VCC = 5 V; differential encode input, unless otherwise noted.
Table 3.
Test
105 MSPS
125 MSPS
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Unit
Encode Rate
Full
IV
10
105
10
125
MSPS
Encode Pulse Width High (tEH)
Full
IV
2.9
2.4
ns
Encode Pulse Width Low (tEL)
Full
IV
2.9
2.4
ns
Aperture Delay (tA)
25°C
V
2.1
ns
Aperture Uncertainty (Jitter)1
25°C
V
0.25
ps rms
Output Valid Time (tV)2
Full
VI
2.5
4.0
2.5
4.0
ns
Output Propagation Delay (tPD)2
Full
VI
4.0
5.5
4.0
5.5
ns
Output Rise Time (tR)2
Full
V
2.1
ns
Output Fall Time (tF)2
Full
V
1.9
ns
Out-of-Range Recovery Time
25°C
V
2
ns
Transient Response Time
25°C
V
2
ns
Latency
Full
IV
10
Cycles
1 Aperture uncertainty includes contribution of the AD9433, crystal clock reference, and encode drive circuit.
2 tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital output swing. The digital output load during testing is not
to exceed an ac load of 10 pF or a dc current of 50 μA. Rise and fall times are measured from 10% to 90%.
TIMING DIAGRAM
tEL
tEH
tA
1/
fS
SAMPLE N – 1
SAMPLE N + 1
SAMPLE N + 8
SAMPLE N + 9
SAMPLE N + 10
SAMPLE N
AIN
ENCODE
tV
tPD
DATA N – 11
DATA N – 10
DATA N – 1
DATA N
DATA N + 1
DATA
N – 9
DATA
N – 2
D11 TO D0
ENCODE
01
97
7-
0
03
Figure 2. Timing Diagram
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