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參數(shù)資料
| 型號： | AD9398/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 43/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9398 |
| 標準包裝： | 1 |
| 主要目的： | 視頻，視頻處理 |
| 已用 IC / 零件： | AD9398 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9398KSTZ-100-ND - IC INTERFACE 100MHZ HDMI 100LQFP AD9398KSTZ-150-ND - IC INTERFACE 150MHZ HDMI 100LQFP |
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AD9398
Rev. 0 | Page 8 of 44
Mnemonic
Description
RTERM
RTERM is the termination resistor used to drive the AD9398 internally to a precise 50 Ω termination for TMDS lines.
This should be a 500 Ω 1% tolerance resistor.
AUDIO DATA OUTPUT
S/PDIF
Sony/Philips Digital Interface. Supports digital audio from 32 kbps to 192 kbps.
I2S0 to I2S3
Inter-IC Sound Channel 0 through Channel 3. Each line supports two channels of digital audio.
MCLKIN
Master Audio Clock External. Used if internal MCLK is not generated.
MCLKOUT
Master Audio Clock Output to Drive Audio DACs.
SCLK
Serial Clock Out to support Digital Audio.
LRCLK
Data Output Clock for Left and Right Audio Channels.
SERIAL PORT
SDA
Serial Port Data I/O for Programming AD9398 Registers—I2C Address is 0x98.
SCL
Serial Port Data Clock for Programming AD9398 Registers.
DDCSDA
Serial Port Data I/O for HDCP Communications to Transmitter—I2C Address is 0x74 or 0x76.
DDCSCL
Serial Port Data Clock for HDCP Communications to Transmitter.
MDA
Serial Port Data I/O to EEPROM with HDCP Keys—I2C Address is 0xA0.
MCL
Serial Port Data Clock to EEPROM with HDCP Keys.
DATA OUTPUTS
RED [7:0]
Data Output, Red Channel.
GREEN [7:0]
Data Output, Green Channel.
BLUE [7:0]
Data Output, Blue Channel.
The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed, but is different if the
color space converter is used. When the sampling time is changed by adjusting the phase register, the output
timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship among the
signals is maintained.
DATA CLOCK OUTPUT
DATACK
Data Clock Output.
This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible
output clocks can be selected with Register 0x25 [7:6]. These are related to the pixel clock (1/2× pixel clock,
1× pixel clock, 2× frequency pixel clock, and a 90° phase shifted pixel clock). They are produced either by the
internal PLL clock generator or EXTCLK and are synchronous with the pixel sampling clock. The polarity of DATACK
can also be inverted via Register 0x24 [0]. The sampling time of the internal pixel clock can be changed by
adjusting the phase register. When this is changed, the pixel-related DATACK timing is shifted as well. The DATA,
DATACK, and HSOUT outputs are all moved, so the timing relationship among the signals is maintained.
POWER SUPPLY1
VD (3.3 V)
Analog Power Supply.
These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible.
VDD (1.8 V
to 3.3 V)
Digital Output Power Supply.
A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply
transients (noise). These supply pins are identified separately from the VD pins, so output noise transferred into the
sensitive analog circuitry can be minimized. If the AD9398 is interfacing with lower voltage logic, VDD may be
connected to a lower supply voltage (as low as 1.8 V) for compatibility.
PVDD (1.8 V)
Clock Generator Power Supply.
The most sensitive portion of the AD9398 is the clock generation circuitry. These pins provide power to the clock
PLL and help the user design for optimal performance. The designer should provide quiet, noise-free power to
these pins.
DVDD (1.8 V)
Digital Input Power Supply.
This supplies power to the digital logic.
GND
Ground.
The ground return for all circuitry on chip. It is recommended that the AD9398 be assembled on a single solid
ground plane, with careful attention to ground current paths.
1 The supplies should be sequenced such that VD and VDD are never less than 300 mV below DVDD. At no time should DVDD be more than 300 mV greater than VD or VDD.
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