參數(shù)資料
型號(hào)： AD9277BSVZ
廠商： Analog Devices Inc
文件頁數(shù)： 28/48頁
文件大?。?/td> 0K
描述： IC ADC 14BIT LNA/VGA/AAF 100TQFP
標(biāo)準(zhǔn)包裝： 1
類型： AAF，ADC，解調(diào)器，LNA，VGA
分辨率（位）： 14 b
采樣率（每秒）： 10M ~ 50M
數(shù)據(jù)接口： 串行，SPI?
電壓電源： 模擬和數(shù)字
電源電壓： 1.8V，3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
配用： AD9277-50EBZ-ND - BOARD EVAL FOR AD9277
AD9277
Rev. 0 | Page 34 of 48
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated as follows:
SNR Degradation = 20 × log10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 68).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9277.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources, such as the Valpey Fisher VFAC3 series.
If the clock is generated from another type of source (by gating,
dividing, or other methods), it should be retimed by the original
clock during the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about how
jitter performance relates to ADCs (visit www.analog.com).
1
10
100
1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.5ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
S
NR
(
d
B
)
08
18
1-
06
2
0.25ps
Figure 68. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 69 and Figure 70, the power dissipated by
the AD9277 is proportional to its sample rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and the bias current of the
LVDS output drivers.
0
SAMPLING FREQUENCY (MSPS)
CURR
E
NT
(
m
A)
300
250
200
150
100
50
10
30
20
40
50
08
18
1-
0
63
IAVDD1
IDRVDD
Figure 69. Supply Current vs. fSAMPLE for fIN = 5 MHz
220
170
0
SAMPLING FREQUENCY (MSPS)
P
O
W
E
R
/C
HANNE
L
(
m
W
)
10
30
20
50
40
215
210
205
200
195
190
185
180
175
08
18
1-
0
64
Figure 70. Power per Channel vs. fSAMPLE for fIN = 5 MHz
The AD9277 features scalable LNA bias currents (see Table 18,
Register 0x12). The default LNA bias current settings are high.
Figure 71 shows the typical reduction of AVDD2 current with
each bias setting. It is also recommended that the LNA offset be
adjusted using Register 0x10 (see Table 18) when the LNA bias
setting is low.
0
50
100
150
200
250
300
350
400
HIGH
L
NA
BI
AS
S
E
T
IN
G
MID-HIGH
MID-LOW
LOW
TOTAL AVDD2 CURRENT (mA)
08
181
-06
5
Figure 71. AVDD2 Current at Different LNA Bias Settings, fSAMPLE = 50 MSPS
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