參數(shù)資料
型號: AD9272BSVZRL-40
廠商: Analog Devices Inc
文件頁數(shù): 33/44頁
文件大?。?/td> 0K
描述: IC ADC ASD OCTAL 40MSPS 100-TQFP
設計資源: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
標準包裝: 1,000
類型: AAF,ADC,交叉點開關,LNA,VGA
分辨率(位): 12 b
采樣率(每秒): 40M
數(shù)據(jù)接口: 串行
電壓電源: 模擬和數(shù)字
電源電壓: 1.8V,3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應商設備封裝: 100-TQFP-EP(14x14)
包裝: 帶卷 (TR)
配用: AD9272-65EBZ-ND - BOARD EVAL AD9272
AD9272
Rev. C | Page 39 of 44
07
02
9-
1
13
NUMBER OF SDIO PINS CONNECTED TOGETHER
V
OH
(V
)
1.715
1.720
1.725
1.730
1.735
1.740
1.745
1.750
1.755
1.760
1.765
1.770
1.775
1.780
1.785
1.790
1.795
1.800
030
20
10
40
50
60
70
80
90
100
Figure 68. SDIO Pin Loading
This interface is flexible enough to be controlled by either serial
PROMS or PIC mirocontrollers. This provides the user with
an alternative method, other than a full SPI controller, for
programming the device (see the AN-812 Application Note).
DON’T CARE
SDIO
SCLK
CSB
tS
tDH
tHI
tCLK
tLO
tDS
tH
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
07
02
9-
0
68
Figure 69. Serial Timing Details
Table 16. Serial Timing Definitions
Parameter
Minimum Timing (ns)
Description
tDS
5
Setup time between the data and the rising edge of SCLK
tDH
2
Hold time between the data and the rising edge of SCLK
tCLK
40
Period of the clock
tS
5
Setup time between CSB and SCLK
tH
2
Hold time between CSB and SCLK
tHI
16
Minimum period that SCLK should be in a logic high state
tLO
16
Minimum period that SCLK should be in a logic low state
tEN_SDIO
10
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 69)
tDIS_SDIO
10
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 69)
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