參數(shù)資料
型號(hào)： AD9253BCPZ-80
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT SRL 80MSPS 48LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： LVDS，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 405mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-WQ（7x7）
包裝： 托盤
輸入數(shù)目和類型： 4 個(gè)差分，雙極
AD9253
Data Sheet
Rev. 0 | Page 28 of 40
Figure 73 shows an example of trace lengths exceeding 24 inches
on standard FR-4 material. Notice that the TIE jitter histogram
reflects the decrease of the data eye opening as the edge deviates
from the ideal position.
It is the user’s responsibility to determine if the waveforms
meet the timing budget of the design when the trace lengths
exceed 24 inches. Additional SPI options allow the user to further
increase the internal termination (increasing the current) of all
four outputs to drive longer trace lengths. This can be achieved
by programming Register 0x15. Even though this produces
sharper rise and fall times on the data edges and is less prone to
bit errors, the power dissipation of the DRVDD supply increases
when this option is used.
500
400
300
200
100
–500
–400
–300
–200
–100
0
–0.8ns
–0.4ns
0ns
0.4ns
–0.8ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(
m
V)
EYE: ALL BITS
ULS: 8000/414024
10k
12k
2k
4k
6k
8k
0k
–800ps –600ps –400ps –200ps
0ps
200ps
400ps
600ps
TI
E
J
ITTE
R
H
IS
T
OG
R
A
M
(
H
it
s)
100
65-
0
76
The format of the output data is twos complement by default.
An example of the output coding format can be found in Table 10.
To change the output data format to offset binary, see the
Memory Map section.
Data from each ADC is serialized and provided on a separate
channel in two lanes in DDR mode. The data rate for each serial
stream is equal to 16 bits times the sample clock rate, with a
maximum of 500 Mbps/lane [(16 bits × 125 MSPS)/(2 × 2) =
500 Mbps/lane)]. The lowest typical conversion rate is 10 MSPS.
See the Memory Map section for details on enabling this feature.
Two output clocks are provided to assist in capturing data from
the AD9253. The DCO is used to clock the output data and is
equal to four times the sample clock (CLK) rate for the default
mode of operation. Data is clocked out of the AD9253 and must
be captured on the rising and falling edges of the DCO that
supports double data rate (DDR) capturing. The FCO is used to
signal the start of a new output byte and is equal to the sample
clock rate in 1× frame mode. See the Timing Diagrams section
for more information.
Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End
Termination Only
Table 10. Digital Output Coding
Input (V)
Condition (V)
Offset Binary Output Mode
Twos Complement Mode
VIN+ VIN
<VREF 0.5 LSB
0000 0000 0000 0000
1000 0000 0000 0000
VIN+ VIN
VREF
0000 0000 0000 0000
1000 0000 0000 0000
VIN+ VIN
0 V
1000 0000 0000 0000
0000 0000 0000 0000
VIN+ VIN
+VREF 1.0 LSB
1111 1111 1111 1100
0111 1111 1111 1100
VIN+ VIN
>+VREF 0.5 LSB
1111 1111 1111 1100
0111 1111 1111 1100
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