參數(shù)資料
型號(hào)： AD9252ABCPZRL7-50
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/52頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT SRL 50MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 14
采樣率（每秒）： 50M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 8
功率耗散（最大）： 773mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 16 個(gè)單端，單極；8 個(gè)差分，單極
AD9252
Data Sheet
Rev. E | Page 32 of 52
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9252 as a system, it
is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9252, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one supply is available, it
should be routed to the AVDD first and then tapped off and
isolated with a ferrite bead or a filter choke preceded by
decoupling capacitors for the DRVDD. The user can employ
several different decoupling capacitors to cover both high and
low frequencies. These capacitors should be located close to the
point of entry at the PC board level and close to the parts with
minimal trace lengths.
A single PC board ground plane should be sufficient when
using the AD9252. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9252. An
exposed continuous copper plane on the PCB should mate to
the AD9252 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
multiple tie points between the ADC and PCB during the
reflow process, whereas using one continuous plane with no
partitions guarantees only one tie point. See Figure 57 for a PCB
layout example. For detailed information on packaging and the
PCB layout of chip scale packages, see the AN-772 Application
Note, A Design and Manufacturing Guide for the Lead Frame
Chip Scale Package (LFCSP).
SILKSCREEN PARTITION
PIN 1 INDICATOR
06296-
034
Figure 57. Typical PCB Layout
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