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參數(shù)資料
| 型號(hào)： | AD9252ABCPZRL7-50 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/52頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SRL 50MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 50M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 功率耗散（最大）： | 773mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 16 個(gè)單端，單極；8 個(gè)差分，單極 |
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AD9252
Data Sheet
Rev. E | Page 18 of 52
For best dynamic performance, the source impedances driving
VIN + x and VIN x should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC. An internal reference buffer
creates the positive and negative reference voltages, REFT and
REFB, respectively, that define the span of the ADC core. The
output common mode of the reference buffer is set to midsupply,
and the REFT and REFB voltages and span are defined as
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD VREF)
Span = 2 × (REFT REFB) = 2 × VREF
It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9252, the largest input span available is 2 V p-p.
Differential Input Configurations
There are several ways to drive the AD9252 either actively or
passively; however, optimum performance is achieved by driving
the analog input differentially. For example, using the AD8334
differential driver to drive the AD9252 provides excellent perfor-
mance and a flexible interface to the ADC (see Figure 39) for
baseband applications. This configuration is commonly used
for medical ultrasound systems.
For applications where SNR is a key parameter, differential
transformer coupling is the recommended input configuration
(see Figure 36 and Figure 37), because the noise performance of
most amplifiers is not adequate to achieve the true performance
of the AD9252.
Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.
2V p-p
R
CDIFF1
C
1CDIFF IS OPTIONAL.
49.9
0.1μF
1k
AGND
AVDD
ADT1-1WT
1:1 Z RATIO
VIN – x
ADC
AD9252
VIN + x
C
06
29
6-
0
18
Figure 36. Differential Transformer-Coupled Configuration
for Baseband Applications
ADC
AD9252
2V p-p
2.2pF
1k
0.1μF
1k
AVDD
ADT1-1WT
1:1 Z RATIO
16nH
0.1μF
16nH
33
499
65
VIN+x
VIN– x
062
96
-01
9
Figure 37. Differential Transformer-Coupled Configuration for IF Applications
Single-Ended Input Configuration
A single-ended input may provide adequate performance in cost-
sensitive applications. In this configuration, SFDR and distortion
performance degrade due to the large input common-mode swing.
If the application requires a single-ended input configuration,
ensure that the source impedances on each input are well matched
in order to achieve the best possible performance. A full-scale input
of 2 V p-p can still be applied to the ADC’s VIN + x pin while the
VIN x pin is terminated. Figure 38 details a typical single-
ended input configuration.
2V p-p
R
49.9
0.1F
AVDD
1k 25
1k
AVDD
VIN – x
ADC
AD9252
VIN + x
CDIFF1
C
1CDIFF IS OPTIONAL.
C
06
296
-02
0
Figure 38. Single-Ended Input Configuration
06
296
-02
1
AD8334
1.0k
374
187
R
C
0.1μF
187
0.1μF
0.1μF10μF
0.1μF
1V p-p
0.1μF
LNA
120nH
VGA
VOH
VIP
INH
22pF
LMD
VIN
LOP
LON
VOL
18nF
274
VIN – x
ADC
AD9252
VIN + x
1k
AVDD
Figure 39. Differential Input Configuration Using the AD8334
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