參數(shù)資料
型號(hào): AD9246BCPZRL7-125
廠商: Analog Devices Inc
文件頁(yè)數(shù): 15/44頁(yè)
文件大?。?/td> 0K
描述: IC ADC 14BIT 125MSPS 48-LFCSP
設(shè)計(jì)資源: Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002)
Driving AD9233/46/54 ADCs in AC-Coupled Baseband Appls (CN0051)
標(biāo)準(zhǔn)包裝: 750
位數(shù): 14
采樣率(每秒): 125M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 3
功率耗散(最大): 425mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 2 個(gè)單端,單極;1 個(gè)差分,單極
AD9246
Rev. A | Page 22 of 44
TIMING
The lowest typical conversion rate of the AD9246 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
The AD9246 provides latched data outputs with a pipeline delay
of 12 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9246. These transients can degrade the dynamic performance
of the converter.
Data Clock Output (DCO)
The AD9246 provides a data clock output (DCO) intended for
capturing the data in an external register. The data outputs are valid
on the rising edge of DCO, unless the DCO clock polarity has
been changed via the SPI. See Figure 2 for a graphical timing
description.
Table 12. Output Data Format
Input (V)
Condition (V)
Binary Output Mode
Twos Complement Mode
Gray Code Mode
(SPI accessible)
OR
VIN+ – VIN–
< –VREF – 0.5 LSB
00 0000 0000 0000
10 0000 0000 0000
11 0000 0000 0000
1
VIN+ – VIN–
= –VREF
00 0000 0000 0000
10 0000 0000 0000
11 0000 0000 0000
0
VIN+ – VIN–
= 0
10 0000 0000 0000
00 0000 0000 0000
0
VIN+ – VIN–
= +VREF – 1.0 LSB
11 1111 1111 1111
01 1111 1111 1111
10 0000 0000 0000
0
VIN+ – VIN–
> +VREF – 0.5 LSB
11 1111 1111 1111
01 1111 1111 1111
10 0000 0000 0000
1
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