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參數(shù)資料
| 型號(hào)： | AD9246BCPZRL7-105 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 105MSPS 48-LFCSP |
| 設(shè)計(jì)資源： | Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002) Driving AD9233/46/54 ADCs in AC-Coupled Baseband Appls (CN0051) |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 350mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，單極 |
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AD9246
Rev. A | Page 29 of 44
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings or
modes allowed on the AD9246 Rev. A evaluation board.
POWER
Connect the switching power supply that is supplied in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P500.
VIN
The evaluation board is set up for a double balun configuration
analog input with optimum 50 Ω impedance matching out to
70 MHz. For more bandwidth response, the differential
capacitor across the analog inputs can be changed or removed
(see Table 8). The common mode of the analog inputs is
developed from the center tap of the transformer via the CML
pin of the ADC (see the Analog Input Considerations section).
VREF
VREF is set to 1.0 V by tying the SENSE pin to ground via
JP507 (Pin 1 and Pin 2). This causes the ADC to operate in
2.0 V p-p full-scale range. A separate external reference option
is also included on the evaluation board. Connect JP507
between Pin 2 and Pin 3, connect JP501, and provide an
external reference at E500. Proper use of the VREF options is
detailed in the Voltage Reference section.
RBIAS
RBIAS requires a 10 kΩ resistor (R503) to ground and is used to
set the ADC core bias current.
CLOCK
The default clock input circuitry is derived from a simple
transformer-coupled circuit using a high bandwidth 1:1 impedance
ratio transformer (T503) that adds a very low amount of jitter to
the clock path. The clock input is 50 Ω terminated and ac-coupled
to handle single-ended sine wave inputs. The transformer converts
the single-ended input to a differential signal that is clipped
before entering the ADC clock inputs.
PDWN
To enable the power-down feature, connect JP506, shorting the
PDWN pin to AVDD.
CSB
The CSB pin is internally pulled up, setting the chip into
external pin mode, to ignore the SDIO and SCLK information.
To connect the control of the CSB pin to the SPI circuitry on the
evaluation board, connect JP1 Pin 1 and Pin 2. To set the chip
into serial pin mode and enable the SPI information on the
SDIO and SCLK pins, tie JP1 low (connect Pin 2 and Pin 3) in
the always enabled mode.
SCLK/DFS
If the SPI port is in external pin mode, the SCLK/DFS pin sets the
data format of the outputs. If the pin is left floating, the pin is
internally pulled down, setting the default condition to binary.
Connecting JP2 Pin 2 and Pin 3 sets the format to twos comple-
ment. If the SPI port is in serial pin mode, connecting JP2 Pin 1
and Pin 2 connects the SCLK pin to the on-board SPI circuitry
(see the Serial Port Interface (SPI) section).
SDIO/DCS
If the SPI port is in external pin mode, the SDIO/DCS pin acts
to set the duty cycle stabilizer. If the pin is left floating, the pin is
internally pulled up, setting the default condition to DCS enabled.
To disable the DCS, connect JP3 Pin 2 and Pin 3. If the SPI port
is in serial pin mode, connecting JP3 Pin 1 and Pin 2 connects the
SDIO pin to the on-board SPI circuitry (see the Serial Port
Interface (SPI) section).
ALTERNATIVE CLOCK CONFIGURATIONS
A differential LVPECL clock can also be used to clock the ADC
input using the AD9515 (U500). When using this drive option,
the components listed in Table 16 need to be populated.
Consult the AD9515 data sheet for more information.
To configure the analog input to drive the AD9515 instead of
the default transformer option, the following components need
to be added, removed, and/or changed.
1.
Remove R507, R508, C532, and C533 in the default
clock path.
2.
Populate R505 with a 0 Ω resistor and C531 in the default
clock path.
3.
Populate R511, R512, R513, R515 to R524, U500, R580,
R582, R583, R584, C536, C537, and R586.
If using an oscillator, two oscillator footprint options are also
available (OSC500) to check the performance of the ADC.
JP508 gives the user flexibility in using the enable pin, which is
common on most oscillators. Populate OSC500, R575, R587,
and R588 to use this option.
ALTERNATIVE ANALOG INPUT DRIVE
CONFIGURATION
This section provides a brief description of the alternative
analog input drive configuration using the AD8352. When
using this particular drive option, some components need to be
differential driver, including how it works and its optional pin
settings, consult the AD8352 data sheet.
To configure the analog input to drive the AD8352 instead of
the default transformer option, the following components need
to be added, removed and/or changed.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9246BCPZRL7-125 | 功能描述:IC ADC 14BIT 125MSPS 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD9246BCPZRL7-80 | 制造商:Analog Devices 功能描述:14-BIT, 80 MSPS/105 MSPS/125 MSPS, 1.8 V ANALOG-TO-DIGITAL C - Tape and Reel |
| AD9248 | 制造商:Analog Devices 功能描述:40 MSPS DUAL A/D CONVERTER - Bulk |
| AD9248-20PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248-40PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
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