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參數(shù)資料
| 型號： | AD9246BCPZRL7-105 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 105MSPS 48-LFCSP |
| 設計資源： | Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002) Driving AD9233/46/54 ADCs in AC-Coupled Baseband Appls (CN0051) |
| 標準包裝： | 750 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 350mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
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AD9246
Rev. A | Page 21 of 44
290
215
0
CLOCK FREQUENCY (MSPS)
P
O
WE
R
(
m
W)
150
0
CU
RRE
NT
(
m
A)
120
90
60
30
80
IDRVDD
IAVDD
TOTAL POWER
05
49
1-
0
91
275
260
245
230
20
40
60
Figure 54. AD9246-80 Power and Current vs. Clock Frequency fIN = 30 MHz
Power-Down Mode
By asserting the PDWN pin high, the AD9246 is placed in
power-down mode. In this state, the ADC typically dissipates
1.8 mW. During power-down, the output drivers are placed in
a high impedance state. Reasserting the PDWN pin low returns
the AD9246 to its normal operational mode. This pin is both
1.8 V and 3.3 V tolerant.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and then must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in power-down mode;
and shorter power-down cycles result in proportionally shorter
wake-up times. With the recommended 0.1 μF decoupling
capacitors on REFT and REFB, it takes approximately 0.25 ms
to fully discharge the reference buffer decoupling capacitors and
0.35 ms to restore full operation.
Standby Mode
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required (see the Memory Map section).
DIGITAL OUTPUTS
The AD9246 output drivers can be configured to interface with
1.8 V to 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operat-
ing in the external pin mode (see Table 10).
As detailed in the Interfacing to High Speed ADCs via SPI User
Manual, the data format can be selected for either offset binary,
twos complement, or Gray code when using the SPI control.
Out-of-Range (OR) Condition
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OR has the same pipeline
latency as the digital data.
05
49
1-
0
88
1
0
1
OR DATA OUTPUTS
OR
+FS – 1 LSB
+FS – 1/2 LSB
+FS
–FS
–FS + 1/2 LSB
–FS – 1/2 LSB
1111
1110
0000
11
00
0000
0001
0000
Figure 55. OR Relation to Input Voltage and Output Data
OR is low when the analog input voltage is within the analog
input range and high when the analog input voltage exceeds the
input range, as shown in Figure 55. OR remains high until the
analog input returns to within the input range, and another conver-
sion is completed. By logically AND’ing the OR bit with the MSB
and its complement, overrange high or underrange low conditions
can be detected. Table 11 is a truth table for the overrange/
underrange circuit in Figure 56, which uses NAND gates.
MSB
OR
MSB
OVER = 1
UNDER = 1
05
49
1-
0
8
7
Figure 56. Overrange/Underrange Logic
Table 11. Overrange/Underrange Truth Table
OR
MSB
Analog Input Is:
0
Within range
0
1
Within range
1
0
Underrange
1
Overrange
Digital Output Enable Function (OEB)
The AD9246 has three-state ability. If the OEB pin is low, the
output data drivers are enabled. If the OEB pin is high, the
output data drivers are placed in a high impedance state. This is
not intended for rapid access to the data bus. Note that OEB is
referenced to the digital supplies (DRVDD) and should not
exceed that supply voltage.
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| AD9246BCPZRL7-125 | 功能描述:IC ADC 14BIT 125MSPS 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9246BCPZRL7-80 | 制造商:Analog Devices 功能描述:14-BIT, 80 MSPS/105 MSPS/125 MSPS, 1.8 V ANALOG-TO-DIGITAL C - Tape and Reel |
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| AD9248-20PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248-40PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
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