參數資料
| 型號： | AD9235BRU-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 40/40頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 65MSPS 28-TSSOP |
| 產品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 1 |
| 位數： | 12 |
| 采樣率（每秒）： | 65M |
| 數據接口： | 并聯 |
| 轉換器數目： | 3 |
| 功率耗散（最大）： | 300mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸入數目和類型： | 2 個單端，單極；1 個差分，單極 |
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Data Sheet
AD9235
Rev. D | Page 9 of 40
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay (tA)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Aperture Jitter (tJ)
The sample-to-sample variation in aperture delay.
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs LSB before the first code transition.
Positive full scale is defined as a level 1 LSBs beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value
LSB below VIN+ = VIN–. Offset error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value LSB
above negative full scale. The last transition should occur at an
analog value 1 LSB below the positive full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at TMIN or TMAX.
Power Supply Rejection Ratio
The change in full scale from the value with the supply
at the minimum limit to the value with the supply at its
maximum limit.
Total Harmonic Distortion (THD)1
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal.
1
AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Signal-to-Noise and Distortion (SINAD)1
The ratio of the rms signal amplitude (set 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents below the Nyquist frequency, including harmonics but
excluding dc.
Effective Number of Bits (ENOB)
The ENOB for a device for sine wave inputs at a given input
frequency can be calculated directly from its measured SINAD
using the following formula
N = (SINAD 1.76)/6.02
Signal-to-Noise Ratio (SNR)1
The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents below the Nyquist frequency, excluding the first six
harmonics and dc.
Spurious-Free Dynamic Range (SFDR)1
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Two-Tone SFDR1
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Clock Pulse Width and Duty Cycle
Pulse-width high is the minimum amount of time that the
clock pulse should be left in the Logic 1 state to achieve rated
performance. Pulse-width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the
guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Output Propagation Delay (tPD)
The delay between the clock logic threshold and the time when
all bits are within valid logic levels.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9235BRURL7-20 | 功能描述:IC ADC 12BIT SGL 20MSPS 28TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| AD9235BRURL7-40 | 功能描述:IC ADC 12BIT SGL 40MSPS 28TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| AD9235BRURL7-65 | 功能描述:IC ADC 12BIT 65MSPS 28-TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| AD9235BRUZ-20 | 功能描述:IC ADC 12BIT 20MSPS 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:microPOWER™ 位數:8 采樣率（每秒）:1M 數據接口:串行，SPI? 轉換器數目:1 功率耗散（最大）:- 電壓電源:模擬和數字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD9235BRUZ-20 | 制造商:Analog Devices 功能描述:IC, ADC, 12BIT, 20MSPS, TSSOP-28 |
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