
AD9235
Data Sheet
Rev. D | Page 22 of 40
WHT
TP7
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
5
7
3
1
HDR40RAM
J1
HEADER
RIGHT
ANGLE
MALE
NO
EJECTORS
OTR
C11
0.1
F
D11
D10
D9
D8
DUTCLK
U7
74VHC541
18
2
11
12
13
14
15
16
17
20
10
19
1
9
8
7
6
5
4
3
AVDD
AVDD; 14
AVDD; 7
2
1
2
5
6
AVDD
JP4
D2
D1
AUXCLK
MC100LVEL33D
U3
6
5
7
8
4
3
2
1
C13
0.1
F
R1
49.9
AVDD
1N5712
A2
A3
A4
A5
A6
A7
A8
G1
G2
GND
VCC
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1
Y1
74VHC04
U8
74VHC04
U8
1N5712
CW
NC
INA
INB
INCOM
VCC
OUT
VEE
REF
U8 DECOUPLING
R19
500
R2
10
R18
500
R7
22
R11
49.9
R15
90
R13
113
R26
10k
R25
10k
C26
0.1
F
C28
10
F
10V
C24
0.1
F
C5
10
F
10V
D5
C12
0.1
F
D3
D2
D1
D0
U6
74VHC541
18
2
11
12
13
14
15
16
17
20
10
19
1
9
8
7
6
5
4
3
2
1
A2
A3
A4
A5
A6
A7
A8
G1
G2
GND
VCC
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1
Y1
C4
10
F
10V
D4
D6
D7
DVDD
RP2 22
8
9
RP2 22
7
10
RP2 22
6
11
RP2 22
5
12
RP2 22
4
13
RP2 22
3
14
RP2 22
2
15
RP2 22
1
16
RP2 22
8
9
RP2 22
7
10
RP2 22
6
11
RP2 22
5
12
RP2 22
4
13
RP2 22
3
14
RP2 22
2
15
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
DACLK
DOTR
DD11
DD10
DD9
DD8
RP2 22
1
16
T2
T1–1T
6
1
2
5
2
1
3
4
S5
CLOCK
1
2
S1
R14
90
R12
113
C27
0.1
F
AVDD
U9 DECOUPLING
C8
10
F
10V
C10
0.1
F
JP9
3
4
74VHC04
U8
JP3
13
12
74VHC04
U8
11
10
U8
9
8
74VHC04
U8
02461-045
R9
22
+
Figure 45. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering