參數資料
型號: AD9229ABCPZ-65
廠商: Analog Devices Inc
文件頁數: 23/40頁
文件大小: 0K
描述: IC ADC 12BIT SRL 65MSPS 48LFCSP
標準包裝: 1
位數: 12
采樣率(每秒): 65M
數據接口: 串行
轉換器數目: 4
功率耗散(最大): 1.47W
電壓電源: 模擬和數字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應商設備封裝: 48-LFCSP-VQ(7x7)
包裝: 托盤
輸入數目和類型: 8 個單端,單極;4 個差分,單極
AD9229
Rev. B | Page 3 of 40
SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 1.
AD9229-50
AD9229-65
Parameter
Temperature
Test
Level
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
12
Bits
ACCURACY
No Missing Codes
Full
VI
Guaranteed
Offset Error
Full
VI
±5
±25
±5
±25
mV
Offset Matching
Full
VI
±5
±25
±5
±25
mV
Gain Error1
Full
VI
±0.3
±2.5
±0.3
±2.5
% FS
Gain Matching1
Full
VI
±0.2
±1.5
±0.2
±1.5
% FS
Differential Nonlinearity (DNL)
25°C
V
±0.3
LSB
Full
VI
±0.3
±0.6
±0.3
±0.7
LSB
Integral Nonlinearity (INL)
25°C
V
±0.6
±0.4
LSB
Full
VI
±0.6
±1
±0.4
±1
LSB
TEMPERATURE DRIFT
Offset Error
Full
V
±2
±3
ppm/°C
Gain Error1
Full
V
±12
ppm/°C
Reference Voltage, VREF = 1 V
Full
V
±16
ppm/°C
REFERENCE
Output Voltage Error, VREF = 1 V
Full
VI
±10
±30
±10
±30
mV
Load Regulation @ 1.0 mA, VREF = 1 V
Full
V
3
mV
Output Voltage Error, VREF = 0.5 V
Full
VI
±8
±17
±8
±17
mV
Load Regulation @ 0.5 mA,
VREF = 0.5 V
Full
V
0.2
mV
Input Resistance
Full
V
7
ANALOG INPUTS
Differential Input Voltage Range
VREF = 1 V
Full
VI
2
V p-p
Differential Input Voltage Range
VREF = 0.5 V
Full
VI
1
V p-p
Common Mode Voltage
Full
V
1.5
V
Input Capacitance2
Full
V
7
pF
Analog Bandwidth, Full Power
Full
V
400
MHz
POWER SUPPLY
AVDD
Full
IV
2.7
3.0
3.6
2.7
3.0
3.6
V
DRVDD
Full
IV
2.7
3.0
3.6
2.7
3.0
3.6
V
IAVDD
Full
VI
300
330
420
455
mA
DRVDD
Full
VI
28
31
29
33
mA
Power Dissipation3
Full
VI
985
1083
1350
1465
mW
Power-Down Dissipation
Full
V
3
mW
CROSSTALK4
Full
V
–95
dB
1 Gain error and gain temperature coefficients are based on the ADC only, with a fixed 1.0 V external reference and a 2 V p-p differential analog input.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.
3 Power dissipation measured with rated encode and 2.4 MHz analog input at –0.5 dBFS.
4 Typical specification over the first Nyquist zone.
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