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| 型號(hào)： | AD9229ABCPZ-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SRL 65MSPS 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 1.47W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；4 個(gè)差分，單極 |
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AD9229
Rev. B | Page 24 of 40
EVALUATION BOARD
The AD9229 evaluation board provides all of the support cir-
cuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially
through a transformer (default) or through the AD8332 driver.
The ADC can also be driven in a single-ended fashion. Separate
power pins are provided to isolate the DUT from the AD8332
drive circuitry. Each input configuration can be selected by
proper connection of various jumpers (see Figure 48 to Figure 52).
Figure 47 shows the typical bench characterization setup used
to evaluate the ac performance of the AD9229. It is critical that
the signal sources used for the analog input and clock have very
low phase noise (<1 ps rms jitter) to realize the ultimate
performance of the converter. Proper filtering of the analog
input signal to remove harmonics and lower the integrated or
broadband noise at the input is also necessary to achieve the
specified noise performance.
plots that demonstrate the routing and grounding techniques
that should be applied at the system level.
POWER SUPPLIES
This evaluation board comes with a wall mountable switching
power supply that provides a 6 V, 2 A maximum output. Simply
connect the supply to the rated 100 V to 240 V ac wall outlet at
47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack
that connects to the PCB at P503. Once on the PC board, the
6 V supply is fused and conditioned before connecting to three
low dropout linear regulators that supply the proper bias to each
of the various sections on the board.
When operating the evaluation board in a nondefault condition,
L504 to L506 can be removed to disconnect the switching
power supply. This enables the user to individually bias each
section of the board. Use P501 to connect a different supply for
each section. At least one 3.0 V supply is needed with a 1 A
current capability for AVDD_DUT and DRVDD_DUT;
however, it is recommended that separate supplies be used for
both analog and digital. To operate the evaluation board using
the VGA option, a separate 5.0 V analog supply is needed in
addition to the other 3.0 V supplies. The 5.0 V supply, or
AVDD_VGA, should have a 1 A current capability as well.
INPUT SIGNALS
When connecting the clock and analog source, use clean signal
generators with low phase noise, such as Rohde & Schwarz SMHU
or HP8644 signal generators or the equivalent. Use 1 m long,
shielded, RG-58, 50 Ω coaxial cable for making connections to
the evaluation board. Dial in the desired frequency and amplitude
within the ADC’s specifications tables. Typically, most ADI
evaluation boards can accept a ~2.8 V p-p or 13 dBm sine wave
input for the clock. When connecting the analog input source, it
is recommended to use a multipole, narrow-band band-pass
filter with 50 Ω terminations. ADI uses TTE, Allen Avionics,
and K&L types of band-pass filters. The filter should be
connected directly to the evaluation board if possible.
OUTPUT SIGNALS
The default setup uses the HSC-ADC-FPGA high speed
deserialization board, which deserializes the digital output data
and converts it to parallel CMOS. These two channels interface
directly with ADI’s standard dual-channel FIFO data capture
board (HSC-ADC-EVALA-DC). Two of the four channels can
then be evaluated at the same time. For more information on
channel settings on these boards and their optional settings,
visit www.analog.com/FIFO.
ROHDE & SCHWARZ,
SMHU,
2V p-p SIGNAL
SYNTHESIZER
ROHDE & SCHWARZ,
SMHU,
2V p-p SIGNAL
SYNTHESIZER
BAND-PASS
FILTER
XFMR
INPUT
CLK
CHA–CHD
12-BIT
SERIAL
LVDS
2 CH
12-BIT
PARALLEL
CMOS
USB
CONNECTION
AD9229
EVALUATION BOARD
HSC-ADC-FPGA
HIGH SPEED
DESERIALIZATION
BOARD
04418-040
HSC-ADC-EVALA-DC
FIFO DATA
CAPTURE
BOARD
PC
RUNNING
ADC
ANALYZER
3.0V
–+
AV
DD_
DUT
DRV
DD_
DUT
GND
–+
5.0V
GND
AV
DD_
V
G
A
3.0V
6V DC
2Amax
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
SWITCHING
POWER
SUPPLY
Figure 47. Evaluation Board Connections
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| AD9229ABCPZRL7-50 | 功能描述:IC ADC 12BIT SRL 50MSPS 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD9229ABCPZRL7-65 | 功能描述:IC ADC 12BIT SRL 65MSPS 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD9229BBC-65 | 制造商:Analog Devices 功能描述:- Bulk |
| ad9229bcp-50 | 制造商:Analog Devices 功能描述: |
| AD9229BCP-65 | 制造商:Analog Devices 功能描述:- Bulk |
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