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參數(shù)資料
| 型號(hào)： | AD9222 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Octal, 12-Bit, 40/50 MSPS Serial LVDS 1.8 V A/D Converter |
| 中文描述： | 八路，12位，40/50 MSPS的串行LVDS 1.8弗吉尼亞州/ D轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 3/56頁(yè) |
| 文件大?。?/td> | 2026K |
| 代理商： | AD9222 |
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AD9222
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = 0.5 dBFS, unless otherwise noted.
Rev. 0 | Page 3 of 56
Table 1.
Parameter
1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference Voltage (1 V Mode)
REFERENCE
Output Voltage Error (VREF = 1 V)
Load Regulation @ 1.0 mA (VREF = 1 V)
Input Resistance
ANALOG INPUTS
Differential Input Voltage Range (VREF = 1 V)
Common-Mode Voltage
Differential Input Capacitance
Analog Bandwidth, Full Power
POWER SUPPLY
AVDD
DRVDD
IAVDD
IDRVDD
Total Power Dissipation (Including Output Drivers)
Power-Down Dissipation
Standby Dissipation
2
CROSSTALK
CROSSTALK (Overrange Condition)
3
1
See the AN-835 Application Note,
Understanding High Speed ADC Testing and Evaluation
, for a complete set of definitions and how these tests were completed.
2
Can be controlled via SPI.
3
Overrange condition is specific with 6 dB of the full-scale input range.
AD9222-40
Typ
Guaranteed
±1
±3
±0.4
±0.3
±0.25
±0.4
±2
±17
±21
±2
3
6
2
AVDD/2
7
325
1.8
1.8
338
51
700
2
83
90
90
AD9222-50
Typ
Guaranteed
±1
±3
±1.5
±0.3
±0.3
±0.4
±2
±17
±21
±2
3
6
2
AVDD/2
7
325
1.8
1.8
357.5
53.5
740
2
89
90
90
Unit
Bits
mV
mV
% FS
% FS
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
mV
mV
kΩ
V p-p
V
pF
MHz
V
V
mA
mA
mW
mW
mW
dB
dB
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
12
Max
Min
12
Max
1.7
1.7
±8
±8
±1.2
±0.7
±0.5
±1
±30
1.9
1.9
348.5
53.6
722
11
1.7
1.7
±8
±8
±2.5
±0.7
±0.65
±1
±30
1.9
1.9
367.5
56.2
760
11
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