參數(shù)資料
型號(hào): AD9222
廠商: Analog Devices, Inc.
英文描述: Octal, 12-Bit, 40/50 MSPS Serial LVDS 1.8 V A/D Converter
中文描述: 八路,12位,40/50 MSPS的串行LVDS 1.8弗吉尼亞州/ D轉(zhuǎn)換器
文件頁數(shù): 27/56頁
文件大?。?/td> 2026K
代理商: AD9222
AD9222
Rev. 0 | Page 27 of 56
90
85
80
75
70
65
60
0
5
10
15
20
25
S
R
BIAS
(k
)
0
SNR
SFDR
Figure 56. SNR/SFDR vs. RBIAS, F
IN
= 10.3 MHz, AD9222-50
0
R
BIAS
(k
)
I
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
5
10
15
20
25
Figure 57. IAVDD vs. RBIAS, AD9222-50
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9222. This is gained up by a factor of 2 internally, setting
V
REF
to 1.0 V, which results in a full-scale differential input span
of 2 V p-p. The V
REF
is set internally by default; however, the
VREF pin can be driven externally with a 1.0 V reference to
achieve more accuracy.
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low ESR capacitors. These capacitors
should be close to the ADC pins and on the same layer of the
PCB as the AD9222. The recommended capacitor values and
configurations for the AD9222 reference pin can be found in
Figure 58.
Table 12. Reference Settings
Selected
Mode
External
Reference
Internal,
2 V p-p FSR
SENSE
Voltage
AVDD
Resulting
VREF (V)
N/A
Resulting
Differential
Span (V p-p)
2 × external
reference
2.0
AGND to 0.2 V
1.0
Internal Reference Operation
A comparator within the AD9222 detects the potential at the
SENSE pin and configures the reference. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 58), setting VREF to 1 V.
The REFT and REFB pins establish their input span of the ADC
core from the reference configuration. The analog input full-
scale range of the ADC equals twice the voltage at the reference
pin for either an internal or an external reference configuration.
If the reference of the AD9222 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 60
depicts how the internal reference voltage is affected by loading.
1μF
0.1μF
V
REF
SENSE
0.5V
REFT
0.1μF
0.1μF
2.2μF
0.1μF
REFB
SELECT
LOGIC
ADC
CORE
+
VIN–
VIN+
0
Figure 58. Internal Reference Configuration
1μF
1
0.1μF
1
V
REF
SENSE
AVDD
0.5V
REFT
0.1μF
0.1μF
2.2μF
0.1μF
REFB
SELECT
LOGIC
ADC
CORE
+
VIN–
VIN+
EXTERNAL
1
OPTIONAL.
0
Figure 59. External Reference Operation
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