參數(shù)資料
型號(hào)： AD9212ABCPZRL7-65
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/56頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT SRL 65MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 10
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 8
功率耗散（最大）： 833mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 16 個(gè)單端，單極；8 個(gè)差分，單極
Data Sheet
AD9212
Rev. E | Page 27 of 56
Two output clocks are provided to assist in capturing data from
the AD9212. The DCO is used to clock the output data and is
equal to five times the sample clock (CLK) rate. Data is clocked
out of the AD9212 and must be captured on the rising and
falling edges of the DCO that supports double data rate (DDR)
capturing. The FCO is used to signal the start of a new output
byte and is equal to the sample clock rate. See the timing
diagram shown in Figure 2 for more information.
Table 9. Flexible Output Test Modes
Output Test
Mode Bit
Sequence
Pattern Name
Digital Output Word 1
Digital Output Word 2
Subject
to Data
Format
Select
0000
Off (default)
N/A
0001
Midscale short
1000 0000 (8-bit)
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
Same
Yes
0010
+Full-scale short
1111 1111 (8-bit)
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
Same
Yes
0011
Full-scale short
0000 0000 (8-bit)
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
Same
Yes
0100
Checkerboard
1010 1010 (8-bit)
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
0101 0101 (8-bit)
01 0101 0101 (10-bit)
0101 0101 0101 (12-bit)
01 0101 0101 0101 (14-bit)
No
0101
PN sequence long1
N/A
Yes
0110
PN sequence short1
N/A
Yes
0111
One-/zero-word toggle
1111 1111 (8-bit)
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
0000 0000 (8-bit)
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
No
1000
User input
Register 0x19 and Register 0x1A
Register 0x1B and Register 0x1C
No
1001
1-/0-bit toggle
1010 1010 (8-bit)
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
N/A
No
1010
1× sync
0000 1111 (8-bit)
00 0001 1111 (10-bit)
0000 0011 1111 (12-bit)
00 0000 0111 1111 (14-bit)
N/A
No
1011
One bit high
1000 0000 (8-bit)
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
N/A
No
1100
Mixed frequency
1010 0011 (8-bit)
10 0110 0011 (10-bit)
1010 0011 0011 (12-bit)
10 1000 0110 0111 (14-bit)
N/A
No
1 All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.
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