參數(shù)資料
型號(hào)： AD9212ABCPZRL7-65
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/56頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT SRL 65MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 10
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 8
功率耗散（最大）： 833mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 16 個(gè)單端，單極；8 個(gè)差分，單極
AD9212
Data Sheet
Rev. E | Page 24 of 56
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(fA) due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 56).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9212.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
1
10
100
1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
S
N
R
(
d
B)
05
96
8-
015
Figure 56. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 57 and Figure 58, the power dissipated by
the AD9212 is proportional to its sample rate. The digital power
dissipation does not vary much because it is determined primarily
by the DRVDD supply and bias current of the LVDS output drivers.
05
96
8-
089
0
0.05
0.10
0.15
0.20
0.25
0.30
10
15
20
25
30
35
40
ENCODE (MHz)
CURRE
NT
(
A)
0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
PO
WER
(
W
)
TOTAL POWER
AVDD CURRENT
DRVDD CURRENT
Figure 57. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, AD9212-40
05
96
8-
090
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
10
20
30
40
50
60
ENCODE (MHz)
CU
RRE
N
T
(
A)
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
PO
W
E
R
(W
)
TOTAL POWER
AVDD CURRENT
DRVDD CURRENT
Figure 58. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, AD9212-65
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9212BCPZ-40 制造商:Analog Devices 功能描述:ADC Octal Pipelined 40Msps 10-bit Serial 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10BIT ADC 40/65MSPS 1.8V SMD 制造商:Analog Devices 功能描述:IC, 10BIT ADC, 40/65MSPS, 1.8V, SMD
AD9212BCPZ-65 制造商:Analog Devices 功能描述:ADC Octal Pipelined 65Msps 10-bit Serial 64-Pin LFCSP EP
AD9212BCPZRL7-40 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
AD9212BCPZRL7-65 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
AD9214 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 65/80/105 MSPS 3 V A/D Converter
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