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參數(shù)資料
| 型號： | AD9200JRSZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT CMOS 20MSPS 28-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
AD9200
–11–
REV. E
The actual reference voltages used by the internal circuitry of
the AD9200 appear on REFTF and REFBF. For proper opera-
tion, it is necessary to add a capacitor network to decouple these
pins. The REFTF and REFBF should be decoupled for all
internal and external configurations as shown in Figure 17.
AD9200
REFTF
REFBF
0.1 F
10 F
0.1 F
Figure 17. Reference Decoupling Network
Note: REFTF = reference top, force
REFBF = reference bottom, force
REFTS = reference top, sense
REFBS = reference bottom, sense
INTERNAL REFERENCE OPERATION
Figures 18, 19 and 20 show example hookups of the AD9200
internal reference in its most common configurations. (Figures
18 and 19 illustrate top/bottom mode while Figure 20 illustrates
center span mode). Figure 29 shows how to connect the AD9200
for 1 V p-p differential operation. Shorting the VREF pin
directly to the REFSENSE pin places the internal reference
amplifier, A1, in unity-gain mode and the resultant reference
output is 1 V. In Figure 18 REFBS is grounded to give an input
range from 0 V to 1 V. These modes can be chosen when the
supply is either +3 V or +5 V. The VREF pin must be bypassed to
AVSS (analog ground) with a 1.0
F tantalum capacitor in
parallel with a low inductance, low ESR, 0.1
F ceramic capacitor.
1V
0V
MODE
AVDD
10k
A/D
CORE
4.2k
TOTAL
REFTS
REFBS
10 F
0.1 F
REFTF
REFBF
0.1 F
AIN
0.1 F
AD9200
10k
REF
SENSE
VREF
A1
1V
A2
SHA
0.1 F
1.0 F
Figure 18. Internal Reference 1 V p-p Input Span
(Top/Bottom Mode)
Figure 19 shows the single-ended configuration for 2 V p-p
operation. REFSENSE is connected to GND, resulting in a 2 V
reference output.
2V
0V
MODE
AVDD
A2
10k
A/D
CORE
4.2k
TOTAL
REFTS
REFBS
10 F
0.1 F
REFTF
REFBF
0.1 F
AIN
0.1 F
AD9200
10k
REF
SENSE
VREF
A1
1V
SHA
0.1 F
1.0 F
Figure 19. Internal Reference, 2 V p-p Input Span
(Top/Bottom Mode)
Figure 20 shows the single-ended configuration that gives the
good high frequency dynamic performance (SINAD, SFDR).
To optimize dynamic performance, center the common-mode
voltage of the analog input at approximately 1.5 V. Connect the
shorted REFTS and REFBS inputs to a low impedance 1.5 V
source. In this configuration, the MODE pin is driven to a volt-
age at midsupply (AVDD/2).
Maximum reference drive is 1 mA. An external buffer is re-
quired for heavier loads.
AVDD/2
+1.5V
2V
1V
MODE
10k
A/D
CORE
4.2k
TOTAL
REFTS
REFBS
10 F
0.1 F
REFTF
REFBF
0.1 F
AIN
0.1 F
AD9200
10k
REF
SENSE
VREF
1V
SHA
A2
A1
0.1 F
1.0 F
Figure 20. Internal Reference 1 V p-p Input Span,
(Center Span Mode)
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